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[00/30] GuC 32.0.3

Message ID 20190329221118.17308-1-michal.wajdeczko@intel.com (mailing list archive)
Headers show
Series GuC 32.0.3 | expand

Message

Michal Wajdeczko March 29, 2019, 10:10 p.m. UTC
New GuC firmwares (for SKL, BXT, KBL, ICL) with updated ABI interface.
Gen9 will only support HuC authentication.
GuC submission is optional only for Gen11. 

Note: we're seeing some issues on specific machines, compare [1] and [2]

[1] https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4030/fi-icl-guc/igt@gem_exec_suspend@basic-s3.html
[2] https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4030/fi-icl-u2/igt@gem_exec_suspend@basic-s3.html


Daniele Ceraolo Spurio (2):
  drm/i915/guc: New GuC IDs based on engine class and instance
  drm/i915/guc: New GuC stage descriptors

Michal Wajdeczko (23):
  drm/i915/guc: Don't allow GuC submission on pre-Gen11
  drm/i915/guc: Simplify preparation of GuC parameter block
  drm/i915/guc: Update GuC firmware versions and names
  drm/i915/guc: Update GuC firmware CSS header
  drm/i915/guc: Update GuC boot parameters
  drm/i915/guc: Update GuC sleep status values
  drm/i915/guc: Update GuC sample-forcewake command
  drm/i915/guc: Always ask GuC to update power domain states
  drm/i915/guc: Update GuC ADS object definition
  drm/i915/guc: Reset GuC ADS during sanitize
  drm/i915/guc: New GuC interrupt register for Gen11
  drm/i915/guc: New GuC scratch registers for Gen11
  drm/i915/guc: Enable GuC CTB communication on Gen11
  drm/i915/huc: New HuC status register for Gen11
  drm/i915/guc: Define GuC firmware version for Icelake
  drm/i915/huc: Define HuC firmware version for Icelake
  drm/i915/guc: Treat GuC initialization failure as -EIO
  drm/i915/guc: New GuC workqueue item submission mechanism
  drm/i915/guc: Add support for resume-parsing wq item
  drm/i915/guc: New reset-engine command
  drm/i915/guc: New engine-reset-complete message
  HAX: prevent CI failures on pre-Gen11 configs with forced GuC
  HAX: Enable HuC

Oscar Mateo (5):
  drm/i915/guc: Update GuC CTB response definition
  drm/i915/guc: Make use of the SW counter field in the context
    descriptor
  drm/i915/guc: Properly capture & release GuC interrupts on Gen11
  drm/i915/guc: Create vfuncs for the GuC interrupts control functions
  drm/i915/guc: Correctly handle GuC interrupts on Gen11

 drivers/gpu/drm/i915/i915_debugfs.c         |  30 +-
 drivers/gpu/drm/i915/i915_drv.h             |  38 +-
 drivers/gpu/drm/i915/i915_gem.c             |   3 +-
 drivers/gpu/drm/i915/i915_gem_context.c     |  15 +-
 drivers/gpu/drm/i915/i915_irq.c             |  94 +++-
 drivers/gpu/drm/i915/i915_params.h          |   2 +-
 drivers/gpu/drm/i915/i915_pci.c             |   1 +
 drivers/gpu/drm/i915/i915_perf.c            |   1 +
 drivers/gpu/drm/i915/i915_reg.h             |   3 +
 drivers/gpu/drm/i915/intel_context_types.h  |   2 +
 drivers/gpu/drm/i915/intel_drv.h            |   3 -
 drivers/gpu/drm/i915/intel_engine_cs.c      |   8 +-
 drivers/gpu/drm/i915/intel_guc.c            | 200 ++++++--
 drivers/gpu/drm/i915/intel_guc.h            |  23 +-
 drivers/gpu/drm/i915/intel_guc_ads.c        | 161 +++---
 drivers/gpu/drm/i915/intel_guc_ads.h        |   1 +
 drivers/gpu/drm/i915/intel_guc_ct.c         |   2 +-
 drivers/gpu/drm/i915/intel_guc_fw.c         |  87 ++--
 drivers/gpu/drm/i915/intel_guc_fwif.h       | 274 +++++-----
 drivers/gpu/drm/i915/intel_guc_reg.h        |  25 +
 drivers/gpu/drm/i915/intel_guc_submission.c | 527 ++++++++++++++++----
 drivers/gpu/drm/i915/intel_huc.c            |  56 ++-
 drivers/gpu/drm/i915/intel_huc_fw.c         |  12 +
 drivers/gpu/drm/i915/intel_lrc.c            |  24 +-
 drivers/gpu/drm/i915/intel_lrc.h            |   4 +
 drivers/gpu/drm/i915/intel_ringbuffer.h     |   2 +
 drivers/gpu/drm/i915/intel_uc.c             |  42 +-
 drivers/gpu/drm/i915/intel_uc_fw.c          |  20 +-
 drivers/gpu/drm/i915/selftests/intel_guc.c  |  16 +-
 29 files changed, 1222 insertions(+), 454 deletions(-)

Comments

Chris Wilson March 30, 2019, 12:49 a.m. UTC | #1
Quoting Patchwork (2019-03-30 00:34:48)
> #### Suppressed ####
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * igt@gem_exec_gttfill@basic:
>     - {fi-icl-guc}:       NOTRUN -> SKIP

What CI doesn't say is that in the 3 runs, each time fi-icl-guc hits the
same deadlock in S3 (gem_exec_susped). intel_uc_suspend? But the trace
isn't conclusive.
-Chris