From patchwork Wed May 8 08:17:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gwan-gyeong Mun X-Patchwork-Id: 10934671 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8B856933 for ; Wed, 8 May 2019 08:18:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7E7E7286D0 for ; Wed, 8 May 2019 08:18:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 72970287AB; Wed, 8 May 2019 08:18:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D0250286D0 for ; Wed, 8 May 2019 08:18:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5279D89226; Wed, 8 May 2019 08:18:00 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7EA4189226; Wed, 8 May 2019 08:17:59 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 May 2019 01:17:59 -0700 X-ExtLoop1: 1 Received: from helsinki.fi.intel.com ([10.237.66.174]) by fmsmga001.fm.intel.com with ESMTP; 08 May 2019 01:17:57 -0700 From: Gwan-gyeong Mun To: intel-gfx@lists.freedesktop.org Date: Wed, 8 May 2019 11:17:51 +0300 Message-Id: <20190508081757.28042-1-gwan-gyeong.mun@intel.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v6 0/6] drm/i915/dp: Support for DP YCbCr4:2:0 outputs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP On Gen 11 platform, to enable resolutions like 5K@120 (or higher) we need to use DSC (DP 1.4) or YCbCr4:2:0 (DP 1.3 or 1.4) on DP. In order to support YCbCr4:2:0 on DP we need to program YCBCR 4:2:0 to MSA and VSC SDP. And Link M/N values are calculated and applied based on the Full Clock forYCbCr420. The Bit per Pixel needs to be adjusted for YUV420 mode as it requires only half of the RGB case. - Link M/N values are calculated and applied based on the Full Clock - Data M/N values needs to be calculated considering the data is half due to subsampling These patches add a VSC structure for handling Pixel Encoding/Colorimetry Formats and program YCBCR 4:2:0 to MSA and VSC SDP. And it changes a link bandwidth computation for DP. These patches tested on below test environment. Test Environment: - Tested System: Gen11 platform - Monitor: Wasabi Mango UHD430 REAL4K HDMI 2.0 Slim HDR DUAL DP i20 (This monitor supports HDMI YCbCr 4:2:0) - DP to HDMI Adaptor (Dongle) : Club3D CAC-1080 (This dongle supports DP YCbCr 4:2:0 pass through feature.) - To enable DP YCbCr 4:2:0 forcely, test enviromnent uses work arounds patches. You can find these on https://gitlab.freedesktop.org/elongbug/drm-tip/tree/dp_ycbcr420_work The idea of a scaling (RGB -> YCbCr4:4:4 -> YCbCr 4:2:0) is to follow the same approach used in YCbCr 4:2:0 on HDMI. v2: Addressed Maarten's review comments, fixed minor coding and block comment style. And reordered a first patch ("drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11") as a last patch. v3: Addressed Ville's review comments. Style fixed with few naming. If lscon is active, it makes not to call intel_dp_ycbcr420_config() to avoid to clobber of lspcon_ycbcr420_config() routine. And it move the 420_only check into the intel_dp_ycbcr420_config(). Remove a changing of pipe_bpp on intel_ddi_set_pipe_settings(). Because the pipe is running at the full bpp, keep pipe_bpp as RGB even though YCbCr 4:2:0 output format is used. Add a link bandwidth computation for YCbCr4:2:0 output format. v4: Fix uninitialized return value which is reported by Dan Carpenter. v5: Addressed reivew comments from Ville. In order to make codes simple, it adds and uses intel_dp_output_bpp() function. In order to avoid the extra indentation, it inverts if-clause on intel_dp_ycbcr420_config(). Remove the error print where no errors print are allowed. v6: Link M/N values are calculated and applied based on the Full Clock for YCbCr420. The Bit per Pixel needs to be adjusted for YUV420 mode as it requires only half of the RGB case. - Link M/N values are calculated and applied based on the Full Clock - Data M/N values needs to be calculated considering the data is half due to subsampling Remove a doubling of pixel clock on a dot clock calculator for DP YCbCr 4:2:0. Rebase and remove a duplicate setting of vsc_sdp.DB17. Add a setting of dynamic range bit to vsc_sdp.DB17. Change Content Type bit to "Graphics" from "Not defined". Change a dividing of pipe_bpp to muliplying to constant values on a switch-case statement. Fix an wrong setting of MSA MISC1 fields for Pixel Encoding/Colorimetry Format indication. As per DP 1.4a spec Table 2-96 [MSA MISC1 and MISC0 Fields for Pixel Encoding/Colorimetry Format Indication] When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the Pixel Encoding/Colorimetry Format. On the wrong version it set a bit 5 of MISC1, now it set a bit 6 of MISC1. References: https://patchwork.freedesktop.org/series/56059/ Gwan-gyeong Mun (6): drm/i915/dp: Add a config function for YCBCR420 outputs drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA drm/i915/dp: Change a link bandwidth computation for DP drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11 drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ddi.c | 12 ++- drivers/gpu/drm/i915/intel_dp.c | 149 ++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_drv.h | 2 + include/drm/drm_dp_helper.h | 17 ++++ 5 files changed, 178 insertions(+), 3 deletions(-)