From patchwork Fri Jun 28 13:07:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11022429 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D329A76 for ; Fri, 28 Jun 2019 13:12:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C4A17286BC for ; Fri, 28 Jun 2019 13:12:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B8B56287A8; Fri, 28 Jun 2019 13:12:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5ADB4286BC for ; Fri, 28 Jun 2019 13:12:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3301A6E91F; Fri, 28 Jun 2019 13:12:33 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id D357F6E91F for ; Fri, 28 Jun 2019 13:12:31 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Jun 2019 06:12:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,427,1557212400"; d="scan'208";a="314131389" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by orsmga004.jf.intel.com with ESMTP; 28 Jun 2019 06:12:28 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Fri, 28 Jun 2019 18:37:44 +0530 Message-Id: <20190628130754.9527-1-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 00/10] DC3CO Support for TGL. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Addressed few review comment provided by Imre on internal mailing list. This series requires Tigerlake platform enablement patches and TGL PSR patches to be merged first, so few patches has commented out original code, which has commented out in order to build the series. DC3CO DMC f/w entry/exit sequence: HSD: https://hsdes.intel.com/appstore/article/#/1405906487 has attached a DC3CO HAS document, HAS document page no.8 has described the DC3CO DMC entry and exit sequence. I am able to validate that DC3CO counter increments on pipe2d emulator. DC5 counter also increment post DC3CO. DC3CO requirements: *Audio codec idle and disabled. *External displays disabled. WD transcoders and DP/HDMI transcoders must be disabled. *Backlight cannot be driven from the display utility pin. It can be driven from the south display. *This feature should be enabled only in Display Video playback on eDP. *DC5 and DC6 not allowed when this feature is enabled. *PSR2 deep sleep disabled (PSR2_CTL Idle Frames = 0000b) *Disable DC3co before mode set, or other Aux, PLL, and DBUF programming, and do not re-enable until after that programming is completed. *DC3co must not be enabled until after PSR2 is enabled. *DC3co must be disabled before PSR2 is disabled. B.Specs: https://gfxspecs.intel.com/Predator/Home/Index/49196 Anshuman Gupta (10): drm/i915/tgl:Added DC3CO required register and bits. i915:Added DC3CO mask to allowed_dc_mask and gen9_dc_mask. i915:Added DC3CO power well. drm/i915/tgl:Added mutual exclusive handling for DC3CO and DC5/6. drm/i915/tgl:Added helper function to prefer dc3co over dc5. drm/i915/tgl:Added VIDEO power domain. drm/i915/tgl:DC3CO PSR2 helper. drm/i915/tgl:switch between dc3co and dc5 based on display idleness. drm/i915/tgl:Added DC3CO counter in i915_dmc_info. drm/i915/tgl: Added new DC5/DC6 counter. drivers/gpu/drm/i915/i915_debugfs.c | 23 ++- drivers/gpu/drm/i915/i915_drv.h | 8 + drivers/gpu/drm/i915/i915_params.c | 3 +- drivers/gpu/drm/i915/i915_reg.h | 13 ++ drivers/gpu/drm/i915/intel_display.c | 45 ++++- drivers/gpu/drm/i915/intel_display.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/i915/intel_pm.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 55 ++++++ drivers/gpu/drm/i915/intel_psr.h | 2 + drivers/gpu/drm/i915/intel_runtime_pm.c | 228 +++++++++++++++++++++++- drivers/gpu/drm/i915/intel_runtime_pm.h | 7 + 12 files changed, 378 insertions(+), 10 deletions(-)