| Message ID | 20190701062632.456-1-animesh.manna@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | DSB enablement. | expand |
On Mon, 01 Jul 2019, Animesh Manna <animesh.manna@intel.com> wrote: > Display State Buffer (DSB) is hardware capability which allows > driver to batch submit HW programming. > > As part of initial enablement common api created which currently used > to program gamma lut proramming. > > Going forwad DSB support can be added for HDR and flip related operation. > > Few changes of this patch series is not tested, sending version 1 > for design review, will be testing in parallel. Our CI reported on the same day that this series oopses on a lot of platforms. Have you investigated and fixed those issues? Please post the fixed series. BR, Jani.
On 8/9/2019 3:12 PM, Jani Nikula wrote: > On Mon, 01 Jul 2019, Animesh Manna <animesh.manna@intel.com> wrote: >> Display State Buffer (DSB) is hardware capability which allows >> driver to batch submit HW programming. >> >> As part of initial enablement common api created which currently used >> to program gamma lut proramming. >> >> Going forwad DSB support can be added for HDR and flip related operation. >> >> Few changes of this patch series is not tested, sending version 1 >> for design review, will be testing in parallel. > Our CI reported on the same day that this series oopses on a lot of > platforms. Have you investigated and fixed those issues? Please post the > fixed series. Found the issue and fixed it (changes added in 15th patch), have sent to trybot, will post the patches soon. Regards, Animesh > > BR, > Jani. >
Display State Buffer (DSB) is hardware capability which allows driver to batch submit HW programming. As part of initial enablement common api created which currently used to program gamma lut proramming. Going forwad DSB support can be added for HDR and flip related operation. Few changes of this patch series is not tested, sending version 1 for design review, will be testing in parallel. HSDES: 1209978241 BSpec: 32020 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Imre Deak <imre.deak@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Shashank Sharma <shashank.sharma@intel.com> Cc: Swati Sharma <swati2.sharma@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Animesh Manna (15): drm/i915/dsb: feature flag added for display state buffer. drm/i915/dsb: DSB context creation. drm/i915/dsb: single register write function for DSB. drm/i915/dsb: Added enum for reg write capability. drm/i915/dsb: Indexed register write function for DSB. drm/i915/dsb: Update i915_write to call dsb-write. drm/i915/dsb: Register definition of DSB registers. drm/i915/dsb: Check DSB engine status. drm/i915/dsb: functions to enable/disable DSB engine. drm/i915/dsb: function to trigger workload execution of DSB. drm/i915/dsb: function to destroy DSB context. drm/i915/dsb: Early prepare of dsb context. drm/i915/dsb: Cleanup of DSB context. drm/i915/dsb: Documentation for DSB. drm/i915/dsb: Enable gamma lut programming using DSB. Documentation/gpu/i915.rst | 9 + drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_color.c | 4 + drivers/gpu/drm/i915/display/intel_display.c | 34 +++ drivers/gpu/drm/i915/i915_drv.h | 9 +- drivers/gpu/drm/i915/i915_reg.h | 53 +++- drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_drv.h | 6 + drivers/gpu/drm/i915/intel_dsb.c | 305 +++++++++++++++++++ drivers/gpu/drm/i915/intel_dsb.h | 48 +++ 10 files changed, 460 insertions(+), 10 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_dsb.c create mode 100644 drivers/gpu/drm/i915/intel_dsb.h