From patchwork Wed Jul 17 10:27:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11047591 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 279F71510 for ; Wed, 17 Jul 2019 10:32:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 17835212D8 for ; Wed, 17 Jul 2019 10:32:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0B9B32870E; Wed, 17 Jul 2019 10:32:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AAA32212D8 for ; Wed, 17 Jul 2019 10:32:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7F98689E5B; Wed, 17 Jul 2019 10:32:16 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3E58889E5B for ; Wed, 17 Jul 2019 10:32:15 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Jul 2019 03:32:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,274,1559545200"; d="scan'208";a="342995122" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by orsmga005.jf.intel.com with ESMTP; 17 Jul 2019 03:32:12 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Wed, 17 Jul 2019 15:57:55 +0530 Message-Id: <20190717102804.27202-1-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 00/10] DC3CO Support for TGL. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This update is a rebased and has addressed few review comment provided by Imre on IRC. DMC f/w DC3CO entry/exit sequence can be found at DC3CO HAS. I am able to validate that DC3CO counter increments on pipe2d emulator. DC5 counter also increment after DC3CO disallow. I will test it on real H/W once it shipped to BA, till then we can finish with review and freeze its design. One patch of this series "0007-drm-i915-tgl-DC3CO-PSR2-helper.patch" will require rebase after https://patchwork.freedesktop.org/series/62416/ series will merged to drm-tip. TGL supports DC3CO only on PipeA in LPSP mpde, so DC3CO doesn't depends on TGL PSR feature on Transcoder B. DC3CO requirements: *Audio codec idle and disabled. *External displays disabled. WD transcoders and DP/HDMI transcoders must be disabled. *Backlight cannot be driven from the display utility pin. It can be driven from the south display. *This feature should be enabled only in Display Video playback on eDP. *DC5 and DC6 not allowed when this feature is enabled. *PSR2 deep sleep disabled (PSR2_CTL Idle Frames = 0000b) *Disable DC3co before mode set, or other Aux, PLL, and DBUF programming, and do not re-enable until after that programming is completed. *DC3co must not be enabled until after PSR2 is enabled. *DC3co must be disabled before PSR2 is disabled. B.Specs:49196 Anshuman Gupta (10): drm/i915/tgl:Added DC3CO required register and bits. i915:Added DC3CO mask to allowed_dc_mask and gen9_dc_mask. i915:Added DC3CO power well. drm/i915/tgl:Added mutual exclusive handling for DC3CO and DC5/6. drm/i915/tgl:Added helper function to prefer dc3co over dc5. drm/i915/tgl:Added VIDEO power domain. drm/i915/tgl:DC3CO PSR2 helper. drm/i915/tgl:switch between dc3co and dc5 based on display idleness. drm/i915/tgl:Added DC3CO counter in i915_dmc_info. drm/i915/tgl:Added new DC5/DC6 counter. drivers/gpu/drm/i915/display/intel_display.c | 39 +++ .../drm/i915/display/intel_display_power.c | 226 +++++++++++++++++- .../drm/i915/display/intel_display_power.h | 10 + drivers/gpu/drm/i915/display/intel_psr.c | 44 ++++ drivers/gpu/drm/i915/display/intel_psr.h | 2 + drivers/gpu/drm/i915/i915_debugfs.c | 17 +- drivers/gpu/drm/i915/i915_drv.h | 8 + drivers/gpu/drm/i915/i915_params.c | 3 +- drivers/gpu/drm/i915/i915_reg.h | 13 + drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/i915/intel_pm.h | 2 + 11 files changed, 357 insertions(+), 9 deletions(-)