From patchwork Tue Sep 3 17:59:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11128529 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EEAA414F7 for ; Tue, 3 Sep 2019 18:02:50 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D6443206BB for ; Tue, 3 Sep 2019 18:02:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D6443206BB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0529489733; Tue, 3 Sep 2019 18:02:49 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9BA948972D for ; Tue, 3 Sep 2019 18:02:47 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Sep 2019 11:02:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,463,1559545200"; d="scan'208";a="382212933" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by fmsmga005.fm.intel.com with ESMTP; 03 Sep 2019 11:02:44 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Tue, 3 Sep 2019 23:29:32 +0530 Message-Id: <20190903175939.6741-1-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v6 0/7] DC3CO Support for TGL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This is a new design proposal for DC3CO feature after disscussing it with Ville and Imre. This design uses a API tgl_set_target_dc_state() API to switch between DC3CO and DC5 by using "DC off" power well. Another major change in this design using page flip frontbuffer flush call to allow DC3CO. As part of DC3CO feature, it needs to configure and enable TRANS_EXITLINE register which only needs to change when transcoder/port is not enabled. It requires to configure and enable it in full modeset sequence. Which requires to force the modeset only at system bootup, with only eDP panel. Tested this series on real H/W, DC3CO counter is validated without any other issue observed. Anshuman Gupta (7): drm/i915/tgl: Add DC3CO required register and bits drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask drm/i915/tgl: Enable DC3CO state in "DC Off" power well drm/i915/tgl: Add helper function for DC3CO exitline. drm/i915/tgl: DC3CO PSR2 helper drm/i915/tgl: switch between dc3co and dc5 based on display idleness drm/i915/tgl: Add DC3CO counter in i915_dmc_info drivers/gpu/drm/i915/display/intel_display.c | 7 + .../drm/i915/display/intel_display_power.c | 305 ++++++++++++++++-- .../drm/i915/display/intel_display_power.h | 15 + .../gpu/drm/i915/display/intel_frontbuffer.c | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 44 +++ drivers/gpu/drm/i915/display/intel_psr.h | 2 + drivers/gpu/drm/i915/i915_debugfs.c | 6 + drivers/gpu/drm/i915/i915_drv.h | 5 + drivers/gpu/drm/i915/i915_params.c | 3 +- drivers/gpu/drm/i915/i915_reg.h | 10 + drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/i915/intel_pm.h | 2 + 12 files changed, 372 insertions(+), 30 deletions(-)