mbox series

[00/11] VRR/Adaptive Sync enabling in i915

Message ID 20201022222709.29386-1-manasi.d.navare@intel.com (mailing list archive)
Headers show
Series VRR/Adaptive Sync enabling in i915 | expand

Message

Navare, Manasi Oct. 22, 2020, 10:26 p.m. UTC
This patch series adds support for DP 1.4 feature of
Adaptive Sync also called as Variable Refresh rate
which is used to match the display rate with the render rate
by stretching or shrinking the blanking time of the frame.


Aditya Swarup (1):
  drm/i915/display/dp: Attach and set drm connector VRR property

Manasi Navare (10):
  drm/i915: Add REG_FIELD_PREP to VRR register def
  drm/i915/display/vrr: Create VRR file and add VRR capability check
  drm/i915/display/dp: Add VRR crtc state variables
  drm/i915/display/dp: Compute VRR state in atomic_check
  drm/i915/display/dp: Do not enable PSR if VRR is enabled
  drm/i915/display/vrr: Configure and enable VRR in modeset enable
  drm/i915/display/vrr: Send VRR push to flip the frame
  drm/i915/display/vrr: Disable VRR in modeset disable path
  drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink
  drm/i915/display: Add HW state readout for VRR

 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |  32 ++++
 drivers/gpu/drm/i915/display/intel_display.c  |  11 +-
 .../drm/i915/display/intel_display_types.h    |   7 +
 drivers/gpu/drm/i915/display/intel_dp.c       |   9 +
 drivers/gpu/drm/i915/display/intel_dp.h       |   1 +
 drivers/gpu/drm/i915/display/intel_psr.c      |   7 +
 drivers/gpu/drm/i915/display/intel_sprite.c   |   5 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 160 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h      |  27 +++
 drivers/gpu/drm/i915/i915_reg.h               |   1 +
 11 files changed, 260 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.h