[0/8] Final set of patches for ADLS enabling

Message

Aditya Swarup Jan. 29, 2021, 6:29 p.m. UTC

These are the final set of patches required for enabling ADL-S. The
patches have been tested on platform and all display outputs are
working.

v2: Address minor nitpicks provided by mdroper.

Patch "drm/i915/adl_s: MCHBAR memory info registers are moved"
can be ignored as Jose's submission 
https://patchwork.freedesktop.org/series/86092/
allows us to fetch dram info from pcode.

Currently in his series, I didn't see removal of
skl_dram_get_channels_info(). So just to get clear results from CI, I
have included the MCHBAR patch in series.

v3:
- Drop MCHBAR patch and rebase on latest drm-tip that adds support for
  reading DRAM info through PCODE.
- Revert to STEP_A0 for Display WA as there is no STEP_A1 for ADLS.

Aditya Swarup (2):
  drm/i915/adl_s: Add display WAs for ADL-S
  drm/i915/adl_s: Add GT and CTX WAs for ADL-S

Anusha Srivatsa (1):
  drm/i915/adl_s: Load DMC

José Roberto de Souza (1):
  drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION

Lucas De Marchi (1):
  drm/i915/adl_s: Add power wells

Matt Roper (2):
  drm/i915/adl_s: Update PHY_MISC programming
  drm/i915/adl_s: Re-use TGL GuC/HuC firmware

Tejas Upadhyay (1):
  drm/i915/adl_s: Update memory bandwidth parameters

 drivers/gpu/drm/i915/display/intel_bw.c       | 11 +++++-
 .../gpu/drm/i915/display/intel_combo_phy.c    | 12 +++++--
 drivers/gpu/drm/i915/display/intel_csr.c      | 10 +++++-
 .../drm/i915/display/intel_display_power.c    |  9 ++---
 drivers/gpu/drm/i915/display/intel_sprite.c   |  6 ++--
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 34 ++++++++++++-------
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c      |  4 ++-
 drivers/gpu/drm/i915/i915_drv.h               |  3 ++
 drivers/gpu/drm/i915/i915_irq.c               |  2 +-
 drivers/gpu/drm/i915/intel_device_info.c      |  8 +++--
 10 files changed, 70 insertions(+), 29 deletions(-)