From patchwork Wed May 11 01:11:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 12845662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E52C9C433EF for ; Wed, 11 May 2022 01:12:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5DB2F10E212; Wed, 11 May 2022 01:12:37 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id EDD8710E212; Wed, 11 May 2022 01:12:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652231557; x=1683767557; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=iy3+5WJwsOnHdm/x0ebakKb2Hlj6xBu6DXfvecRK7wk=; b=PfWJtn5ymNxIzaV5mJctMEPdsVckXNOY33r4T0hfMzzF3dpBU0pVE0Ek LCxwsA8KqNgq7e4OguXxI1Sm+0eKxJKLDn3uNgSSRldIuZyomXLUbptGx UB+zhVpCgxdYlKqzHoMEBh4pPp+82r6xo5K7+EVVNaPXI9B6UloDPtHI5 fpVr0t2iSDmsPYEWJblkXTOcsPIKaBaDzZ/G5v1c9ff0LA4m+1IHv9OZs J1qdBLdZ8quxx7sqvFKprPABDQmPsjTihJyGs2f2itgG1X6ovlCQc3nOR LuINX383yTOwMFdvm++nFtXveCaZExkz0ff2vA5SupATXcHHjWM+HTGj9 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="250080608" X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="250080608" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 18:12:02 -0700 X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="593842577" Received: from ymmonter-mobl.amr.corp.intel.com (HELO intel.com) ([10.249.32.19]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 18:11:31 -0700 From: Andi Shyti To: Intel GFX , DRI Devel Date: Wed, 11 May 2022 03:11:18 +0200 Message-Id: <20220511011121.114226-1-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 0/3] Clear TLB caches in all tiles when object is removed X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Auld , Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Hi, Maybe I should not send patches this late at night as I end up messing things up and spamming sleeping people. Sorry for this version 4. The real fix is in patch 2. The rest is a helper that adds the with_intel_gt_pm_if_awake() (from Chris) and one more check on the status of the engine before accessing it for clearing the TLB. Andi Changelog ========= v3 -> v4 - Fix e-mail mismatch in author and in SoB (Sorry!). v2 -> v3 (v2: https://patchwork.freedesktop.org/series/103835/) - Add missing header file that was causing a compmile error. - Fix wrong patch formatting. v1 -> v2 (v1: https://patchwork.freedesktop.org/series/103831/) - Add with_intel_gt_pm_if_awake() macro for gt specific wakeref. - Check if an engine is awake before invalidating its TLB. Andi Shyti (2): drm/i915/gem: Flush TLBs for all the tiles when clearing an obj drm/i915/gt: Skip TLB invalidation if the engine is not awake Chris Wilson (1): drm/i915/gt: Ignore TLB invalidations on idle engines drivers/gpu/drm/i915/gem/i915_gem_pages.c | 12 +++++++++--- drivers/gpu/drm/i915/gt/intel_gt.c | 4 ++++ drivers/gpu/drm/i915/gt/intel_gt_pm.h | 4 ++++ 3 files changed, 17 insertions(+), 3 deletions(-)