[v2,00/12] small BAR uapi bits

Message ID	20220621104434.190962-1-matthew.auld@intel.com (mailing list archive)
Headers	show Return-Path: <intel-gfx-bounces@lists.freedesktop.org> From: Matthew Auld <matthew.auld@intel.com> To: intel-gfx@lists.freedesktop.org Date: Tue, 21 Jun 2022 11:44:22 +0100 Message-Id: <20220621104434.190962-1-matthew.auld@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Intel-gfx] [PATCH v2 00/12] small BAR uapi bits Precedence: list Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	small BAR uapi bits \| expand [v2,00/12] small BAR uapi bits [v2,01/12] drm/doc: add rfc section for small BAR uapi [v2,02/12] drm/i915/uapi: add probed_cpu_visible_size [v2,03/12] drm/i915/uapi: expose the avail tracking [v2,04/12] drm/i915: remove intel_memory_region avail [v2,05/12] drm/i915/uapi: apply ALLOC_GPU_ONLY by default [v2,06/12] drm/i915/uapi: add NEEDS_CPU_ACCESS hint [v2,07/12] drm/i915/error: skip non-mappable pages [v2,08/12] drm/i915/uapi: tweak error capture on recoverable contexts [v2,09/12] drm/i915/selftests: ensure we reserve a fence slot [v2,10/12] drm/i915/ttm: handle blitter failure on DG2 [v2,11/12] drm/i915: turn on small BAR support [v2,12/12] HAX: force small BAR on dg2

Message ID

20220621104434.190962-1-matthew.auld@intel.com (mailing list archive)

Headers

From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Date: Tue, 21 Jun 2022 11:44:22 +0100
Message-Id: <20220621104434.190962-1-matthew.auld@intel.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Subject: [Intel-gfx] [PATCH v2 00/12] small BAR uapi bits
Precedence: list
Cc: dri-devel@lists.freedesktop.org
Errors-To: intel-gfx-bounces@lists.freedesktop.org
Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>

Series

small BAR uapi bits | expand

Test-with: 20220621103001.184373-1-matthew.auld@intel.com IGT: https://patchwork.freedesktop.org/series/104368/#rev2 Mesa: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16739 (WIP)