Message ID | 20230105125446.960504-1-mika.kahola@intel.com (mailing list archive) |
---|---|
Headers | show
Return-Path: <intel-gfx-bounces@lists.freedesktop.org> X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F41C6C3DA7D for <intel-gfx@archiver.kernel.org>; Thu, 5 Jan 2023 12:59:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7DB7B10E710; Thu, 5 Jan 2023 12:59:36 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id CDBC110E710 for <intel-gfx@lists.freedesktop.org>; Thu, 5 Jan 2023 12:59:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672923574; x=1704459574; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=S9iY69Dg2LPZebBCYwHiCQl0MFTXe4kt4sVqQgWQowg=; b=EFPPQoPdiE/rVQLPj5ZO4UA+n6GEoF/367dA5RMpgrtQhQblgeWvF4jl Ire2vRsZFEzfemzs9x7PDFFgcx/l6/qibFH29IL/DqZ5PpNwrkZqfOiTX 0r57gc13GVac48Rf5feXf4qaSJRemIeiSOokW91Kuy7atF1ch3BY7tlFN 68jPYHiM9PEAnGrbpmXVrO3KugHxH2GT5NdOjxYexkEmMnd7CkuG0EslE SkG8XP6MY5zmOJYG5LY201Ljpa3K2mqSdZLoJ4iAsKXYGInrEqZVKkFEu G4PfOpNG0RRNXXc/p14e4weXjO7EAiyCsLMc0MRkP0NhQfGy4aGNmILg8 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="305697702" X-IronPort-AV: E=Sophos;i="5.96,303,1665471600"; d="scan'208";a="305697702" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2023 04:59:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10580"; a="829540933" X-IronPort-AV: E=Sophos;i="5.96,303,1665471600"; d="scan'208";a="829540933" Received: from sorvi2.fi.intel.com ([10.237.72.194]) by orsmga005.jf.intel.com with ESMTP; 05 Jan 2023 04:59:32 -0800 From: Mika Kahola <mika.kahola@intel.com> To: intel-gfx@lists.freedesktop.org Date: Thu, 5 Jan 2023 14:54:25 +0200 Message-Id: <20230105125446.960504-1-mika.kahola@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Intel-gfx] [PATCH v2 00/21] drm/i915/mtl: Add C10 and C20 phy support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development <intel-gfx.lists.freedesktop.org> List-Unsubscribe: <https://lists.freedesktop.org/mailman/options/intel-gfx>, <mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe> List-Archive: <https://lists.freedesktop.org/archives/intel-gfx> List-Post: <mailto:intel-gfx@lists.freedesktop.org> List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help> List-Subscribe: <https://lists.freedesktop.org/mailman/listinfo/intel-gfx>, <mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe> Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org> |
Series |
drm/i915/mtl: Add C10 and C20 phy support
|
expand
|
PHY programming support for PICA C10 and C20 Type-C chips. v2: Move intel_cx0_reg_defs.h to intel_cx0_phy_regs.h (Jani) Move pmdemand as part of intel_display structure PLL table updates Signed-off-by: Mika Kahola <mika.kahola@intel.com> Anusha Srivatsa (1): drm/i915/mtl: Pin assignment for TypeC Clint Taylor (1): drm/i915/mtl: Initial DDI port setup Gustavo Sousa (1): drm/i915/mtl: Define mask for DDI AUX interrupts Imre Deak (1): drm/i915/mtl: TypeC HPD live status query Mika Kahola (14): drm/i915/mtl: Add DP rates drm/i915/mtl: Create separate reg file for PICA registers drm/i915/mtl: Add support for PM DEMAND drm/i915/mtl: C20 PLL programming drm/i915/mtl: C20 HW readout drm/i915/mtl: C20 port clock calculation drm/i915/mtl: C20 HDMI state calculations drm/i915/mtl: Add voltage swing sequence for C20 drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll drm/i915/mtl: Readout Thunderbolt HW state drm/i915/mtl: Enable TC ports drm/i915/mtl: MTL PICA hotplug detection drm/i915/mtl: Power up TCSS Radhakrishna Sripada (3): drm/i915/mtl: Add Support for C10 PHY message bus and pll programming drm/i915/mtl: Add C10 phy programming for HDMI drm/i915/mtl: Add vswing programming for C10 phys drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_bw.c | 4 +- drivers/gpu/drm/i915/display/intel_bw.h | 2 + drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2702 +++++++++++++++++ drivers/gpu/drm/i915/display/intel_cx0_phy.h | 57 + .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 212 ++ drivers/gpu/drm/i915/display/intel_ddi.c | 37 +- .../drm/i915/display/intel_ddi_buf_trans.c | 65 +- .../drm/i915/display/intel_ddi_buf_trans.h | 6 + drivers/gpu/drm/i915/display/intel_display.c | 26 +- .../gpu/drm/i915/display/intel_display_core.h | 6 + .../drm/i915/display/intel_display_power.c | 11 +- .../i915/display/intel_display_power_map.c | 1 + .../i915/display/intel_display_power_well.c | 2 +- .../drm/i915/display/intel_display_types.h | 23 + drivers/gpu/drm/i915/display/intel_dp.c | 23 +- drivers/gpu/drm/i915/display/intel_dpll.c | 22 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 7 +- drivers/gpu/drm/i915/display/intel_hdmi.h | 1 + .../drm/i915/display/intel_modeset_verify.c | 2 + drivers/gpu/drm/i915/display/intel_tc.c | 177 +- drivers/gpu/drm/i915/i915_irq.c | 253 +- drivers/gpu/drm/i915/i915_reg.h | 69 +- drivers/gpu/drm/i915/i915_reg_defs.h | 57 + drivers/gpu/drm/i915/intel_pm.c | 286 ++ drivers/gpu/drm/i915/intel_pm.h | 35 + 27 files changed, 4062 insertions(+), 27 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.c create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.h create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h