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[0/2] C20 Computed HDMI TMDS pixel clocks

Message ID 20230505184640.2200251-1-clinton.a.taylor@intel.com (mailing list archive)
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Series C20 Computed HDMI TMDS pixel clocks | expand

Message

Clint Taylor May 5, 2023, 6:46 p.m. UTC 
Use computed C20 HDMI TMDS pixel clocks to support 25.175MHz to
594000MHz modes. Add 16 Bit mask operators to support C20 phy
programming.

BSPEC: 64568
Cc: Imre Deak <imre.deak@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com>  

Clint Taylor (2):
  drm/i915: Add 16bit register/mask operators
  drm/i915/hdmi: C20 computed PLL frequencies

 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 89 +++++++++++++++++--
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 53 +++++++++++
 drivers/gpu/drm/i915/i915_reg_defs.h          | 49 ++++++++++
 3 files changed, 185 insertions(+), 6 deletions(-)