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[0/6] drm/i915: VRR and M/N stuff

Message ID 20230828054140.28054-1-ville.syrjala@linux.intel.com (mailing list archive)
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Series drm/i915: VRR and M/N stuff | expand

Message

Ville Syrjala Aug. 28, 2023, 5:41 a.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Some prep work towards reconciling VRR and M/N. I think after these
we coukd try VRR fastsets that alter the state of the VRR registers,
assuming we toggle VRR off and on around the update.

Cc: Manasi Navare <navaremanasi@chromium.org>

Ville Syrjälä (6):
  drm/i915: Move psr unlock out from the pipe update critical section
  drm/i915: Change intel_pipe_update_{start,end}() calling convention
  drm/i915: Extract intel_crtc_vblank_evade_scanlines()
  drm/i915: Enable VRR later during fastsets
  drm/i915: Adjust seamless_m_n flag behaviour
  drm/i915: Optimize out redundant M/N updates

 drivers/gpu/drm/i915/display/intel_atomic.c   |   1 +
 drivers/gpu/drm/i915/display/intel_crtc.c     | 105 +++++++++++-------
 drivers/gpu/drm/i915/display/intel_crtc.h     |   6 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  45 +++++---
 .../drm/i915/display/intel_display_types.h    |   2 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |   2 +-
 6 files changed, 101 insertions(+), 60 deletions(-)