| Message ID | 20230901130440.2085-1-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | drm/i915: VRR, LRR, and M/N stuff | expand |
Hi Ville, After the comments have been addressed, I have completed reviewing the patches. Is there anything else blocking this from getting merged? Could we get this merged if everything looks good? Regards Manasi On Fri, Sep 1, 2023 at 6:04 AM Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Attempt to make VRR, LRR, and M/N updates coexist nicely, > allowing fastsets whenever feasible. > > Lightly smoke tested on my adl. > > Cc: Manasi Navare <navaremanasi@chromium.org> > > Ville Syrjälä (12): > drm/i915: Move psr unlock out from the pipe update critical section > drm/i915: Change intel_pipe_update_{start,end}() calling convention > drm/i915: Extract intel_crtc_vblank_evade_scanlines() > drm/i915: Enable VRR later during fastsets > drm/i915: Adjust seamless_m_n flag behaviour > drm/i915: Optimize out redundant M/N updates > drm/i915: Relocate is_in_vrr_range() > drm/i915: Validate that the timings are within the VRR range > drm/i915: Disable VRR during seamless M/N changes > drm/i915: Update VRR parameters in fastset > drm/i915: Assert that VRR is off during vblank evasion if necessary > drm/i915: Implement transcoder LRR for TGL+ > > drivers/gpu/drm/i915/display/intel_atomic.c | 2 + > drivers/gpu/drm/i915/display/intel_crtc.c | 110 ++++++++------ > drivers/gpu/drm/i915/display/intel_crtc.h | 6 +- > drivers/gpu/drm/i915/display/intel_display.c | 135 ++++++++++++++---- > .../drm/i915/display/intel_display_device.h | 1 + > .../drm/i915/display/intel_display_types.h | 5 +- > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > drivers/gpu/drm/i915/display/intel_panel.c | 17 +-- > drivers/gpu/drm/i915/display/intel_vrr.c | 18 ++- > drivers/gpu/drm/i915/display/intel_vrr.h | 1 + > drivers/gpu/drm/i915/i915_reg.h | 1 + > 11 files changed, 212 insertions(+), 86 deletions(-) > > -- > 2.41.0 >
On Wed, Sep 20, 2023 at 11:54:41AM -0700, Manasi Navare wrote: > Hi Ville, > > After the comments have been addressed, I have completed reviewing the > patches. Is there anything > else blocking this from getting merged? Could we get this merged if > everything looks good? Series pushed to drm-intel-next, Thanks for the reviews everyone. > > Regards > Manasi > > On Fri, Sep 1, 2023 at 6:04 AM Ville Syrjala > <ville.syrjala@linux.intel.com> wrote: > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Attempt to make VRR, LRR, and M/N updates coexist nicely, > > allowing fastsets whenever feasible. > > > > Lightly smoke tested on my adl. > > > > Cc: Manasi Navare <navaremanasi@chromium.org> > > > > Ville Syrjälä (12): > > drm/i915: Move psr unlock out from the pipe update critical section > > drm/i915: Change intel_pipe_update_{start,end}() calling convention > > drm/i915: Extract intel_crtc_vblank_evade_scanlines() > > drm/i915: Enable VRR later during fastsets > > drm/i915: Adjust seamless_m_n flag behaviour > > drm/i915: Optimize out redundant M/N updates > > drm/i915: Relocate is_in_vrr_range() > > drm/i915: Validate that the timings are within the VRR range > > drm/i915: Disable VRR during seamless M/N changes > > drm/i915: Update VRR parameters in fastset > > drm/i915: Assert that VRR is off during vblank evasion if necessary > > drm/i915: Implement transcoder LRR for TGL+ > > > > drivers/gpu/drm/i915/display/intel_atomic.c | 2 + > > drivers/gpu/drm/i915/display/intel_crtc.c | 110 ++++++++------ > > drivers/gpu/drm/i915/display/intel_crtc.h | 6 +- > > drivers/gpu/drm/i915/display/intel_display.c | 135 ++++++++++++++---- > > .../drm/i915/display/intel_display_device.h | 1 + > > .../drm/i915/display/intel_display_types.h | 5 +- > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > > drivers/gpu/drm/i915/display/intel_panel.c | 17 +-- > > drivers/gpu/drm/i915/display/intel_vrr.c | 18 ++- > > drivers/gpu/drm/i915/display/intel_vrr.h | 1 + > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > 11 files changed, 212 insertions(+), 86 deletions(-) > > > > -- > > 2.41.0 > >
From: Ville Syrjälä <ville.syrjala@linux.intel.com> Attempt to make VRR, LRR, and M/N updates coexist nicely, allowing fastsets whenever feasible. Lightly smoke tested on my adl. Cc: Manasi Navare <navaremanasi@chromium.org> Ville Syrjälä (12): drm/i915: Move psr unlock out from the pipe update critical section drm/i915: Change intel_pipe_update_{start,end}() calling convention drm/i915: Extract intel_crtc_vblank_evade_scanlines() drm/i915: Enable VRR later during fastsets drm/i915: Adjust seamless_m_n flag behaviour drm/i915: Optimize out redundant M/N updates drm/i915: Relocate is_in_vrr_range() drm/i915: Validate that the timings are within the VRR range drm/i915: Disable VRR during seamless M/N changes drm/i915: Update VRR parameters in fastset drm/i915: Assert that VRR is off during vblank evasion if necessary drm/i915: Implement transcoder LRR for TGL+ drivers/gpu/drm/i915/display/intel_atomic.c | 2 + drivers/gpu/drm/i915/display/intel_crtc.c | 110 ++++++++------ drivers/gpu/drm/i915/display/intel_crtc.h | 6 +- drivers/gpu/drm/i915/display/intel_display.c | 135 ++++++++++++++---- .../drm/i915/display/intel_display_device.h | 1 + .../drm/i915/display/intel_display_types.h | 5 +- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_panel.c | 17 +-- drivers/gpu/drm/i915/display/intel_vrr.c | 18 ++- drivers/gpu/drm/i915/display/intel_vrr.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 1 + 11 files changed, 212 insertions(+), 86 deletions(-)