| Message ID | 20240301084503.2971826-1-mitulkumar.ajitkumar.golani@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Enable Adaptive Sync SDP Support for DP | expand |
On Fri, 01 Mar 2024, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote: > An Adaptive-Sync-capable DP protocol converter indicates its > support by setting the related bit in the DPCD register. Please stop sending new series all the time! Let the review come to a natural stop, with all the review comments gathered, and issues fixed, before sending a new version. Don't send another version until *all* patches in the series have gotten either R-b or actionable review comments. Sending new versions in short succession actually harms your series getting merged instead of helps, because it scatters the review comments and discussion to multiple threads that are difficult to follow. You also haven't added the Reviewed-by's for the patches that actually have been reviewed. Whoever applies this would have to go through the old threads to find out which patches got reviewed, and if they match the latest thread. And any potential reviewer might not know some of the patches have already been reviewed, and might do duplicate work. For a series of this size, please send at most 1-2 new revisions per *week*, unless you're sure all the pathes have gotten review and the series should be ready to merge. Make each new revision count. BR, Jani.
An Adaptive-Sync-capable DP protocol converter indicates its support by setting the related bit in the DPCD register. Computes AS SDP values based on the display configuration, ensuring proper handling of Variable Refresh Rate (VRR) in the context of Adaptive Sync. --v2: - Update logging to Patch-1 - use as_sdp instead of async - Put definitions to correct placeholders from where it is defined. - Update member types of as_sdp for uniformity. - Correct use of REG_BIT and REG_GENMASK. - Remove unrelated comments and changes. - Correct code indents. - separate out patch changes for intel_read/write_dp_sdp. --v3: - Add VIDEO_DIP_ASYNC_DATA_SIZE definition and comment in as_sdp_pack function to patch 2 as originally used there. [Patch 2]. - Add VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes [Patch 3]. --v4: - Add check for HAS_VRR before writing AS SDP. [Patch 3]. --v5: - Add missing check for HAS_VRR before reading AS SDP as well [Patch 3]. --v6: - Rebase all patches. - Compute TRANS_VRR_VSYNC. -v7: - Move vrr_vsync_start/end to compute config. - Use correct function for drm_debug_printer. -v8: - Code refactoring. - Update, VSYNC_START/END macros to VRR_VSYNC_START/END.(Ankit) - Update bit fields of VRR_VSYNC_START/END.(Ankit) - Send patches to dri-devel.(Ankit) - Update definition names for AS SDP which are starting from HSW, as these defines are applicable for ADLP+.(Ankit) - Remove unused bitfield define, AS_SDP_ENABLE. - Add support in drm for Adaptive Sync sink status, which can be used later as a check for read/write sdp. (Ankit) -v9: - Add enum to operation mode to represent different AVT and FAVT modes. (Ankit) - Operation_mode, target_rr etc should be filled from as_sdp struct. (Ankit) - Fill as_sdp->*All Params* from compute config, read from the sdp. (Ankit) - Move configs to the appropriate patch where it used first.(Ankit) - There should be a check if as sdp is enable is set or not. (Ankit) - Add variables in crtc state->vrr for ad sdp enable and operation mode. (Ankit) - Use above variables for tracking AS SDP. (Ankit) - Revert unused changes. (Ankit) -v10: - Send Patches to dri-devel (Ankit). -v11: - Remove as_sdp_mode and enable from crtc_state. - For consistency, update ADL_ prefix or post fix as required. - Add a comment mentioning current support of DP_AS_SDP_AVT_FIXED_VTOTAL. - Add state checker for AS_SDP infoframe enable. - Add PIPE_CONF_CHECK_I(vrr.vsync_start/end). - Read/write vrr_vsync params only when we intend to send adaptive_sync sdp. -v12: - Update cover letter -v13: - Add correct place holder and name change for AS_SDP_OP_MODE. - Separate i915 changes from drm changes. - Remove extra lines. - Check if AS_SDP bit is set in crtc_state->infoframes.enable. If not return. - Check for HAS_AS_SDP() before setting VIDEO_DIP_ENABLE_AS_ADL mask. - Just use drm/i915/dp in subject line. - Drop conn_state from intel_dp_compute_as_sdp, as not used. - Remove fullstop in subject line. - crtc_state->infoframes.enable, to add on correct place holder. --v14: - Mistakenly dropped first patch, adding back. --v15: - Rename intel_read_dp_infoframe_as_sdp to intel_read_dp_as_sdp. - Add an entry in g4x_infoframe_enable. - Instead of intel_vrr_is_in_range, use crtc_state->vrr.enable in AS SDP compute config. Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Mitul Golani (9): drm/dp: Add support to indicate if sink supports AS SDP drm: Add Adaptive Sync SDP logging drm: Add crtc state dump for Adaptive Sync SDP drm/i915/dp: Add Read/Write support for Adaptive Sync SDP drm/i915/dp: Add wrapper function to check AS SDP drm/i915/display: Compute AS SDP parameters drm/i915/display: Add state checker for Adaptive Sync SDP drm/i915/display: Compute vrr_vsync params drm/i915/display: Read/Write AS sdp only when sink/source has enabled drivers/gpu/drm/display/drm_dp_helper.c | 37 +++++ .../drm/i915/display/intel_crtc_state_dump.c | 13 ++ drivers/gpu/drm/i915/display/intel_ddi.c | 1 + drivers/gpu/drm/i915/display/intel_display.c | 48 +++++++ .../drm/i915/display/intel_display_device.h | 1 + .../drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/display/intel_dp.c | 126 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_hdmi.c | 14 +- drivers/gpu/drm/i915/display/intel_vrr.c | 29 +++- drivers/gpu/drm/i915/i915_reg.h | 15 +++ include/drm/display/drm_dp.h | 10 ++ include/drm/display/drm_dp_helper.h | 30 +++++ 13 files changed, 324 insertions(+), 3 deletions(-)