[0/3] LunarLake IO and Fast Wake changes

Message

Hogander, Jouni May 3, 2024, 6:06 a.m. UTC

There are some changes in LunarLake IO and Fast Wake configuration:

IO Wake Lines configuration is now 6 bits wide
Fast Wake Lines configuration is now 6 bits wide and in ALPM_CTL register
PSR2_CTL[Block count number] is not valid for LunarLake and onwards

This patch set modifies the driver accordingly.

Jouni Högander (3):
  drm/i915/psr: LunarLake IO and Fast Wake time line count maximums are
    63
  drm/i915/psr: LunarLake PSR2_CTL[IO Wake Lines] is 6 bits wide
  drm/i915/psr: PSR2_CTL[Block Count Number] no needed for LunarLake

 drivers/gpu/drm/i915/display/intel_psr.c      | 9 ++++++---
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++++
 2 files changed, 10 insertions(+), 3 deletions(-)