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[0/4] drm/i915/dsb: Try to fix CPU MMIO fails during legacy LUT updates

Message ID 20241120164123.12706-1-ville.syrjala@linux.intel.com (mailing list archive)
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Series drm/i915/dsb: Try to fix CPU MMIO fails during legacy LUT updates | expand

Message

Ville Syrjala Nov. 20, 2024, 4:41 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The current approach of using non-posted DSB writes for the legacy
LUT updats is causing CPU MMIO accesses to fail while the palette
anti-collision logic is active. Try to avoid the problem by swithing
to double posted writes and speeding up the update in other ways.

Ville Syrjälä (4):
  drm/i915/dsb: Don't use indexed register writes needlessly
  drm/i915/color: Stop using non-posted DSB writes for legacy LUT
  drm/i915/dsb: Nuke the MMIO->indexed register write logic
  drm/i915: Do state check for color management changes

 drivers/gpu/drm/i915/display/intel_color.c    | 81 ++++++++++++-------
 drivers/gpu/drm/i915/display/intel_dsb.c      | 73 +++++++----------
 drivers/gpu/drm/i915/display/intel_dsb.h      |  2 +
 .../drm/i915/display/intel_modeset_verify.c   |  2 +
 4 files changed, 83 insertions(+), 75 deletions(-)