| Message ID | 20250120042122.1029481-1-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add HDMI PLL Algorithm for SNPS/C10PHY | expand |
Thank You for the series. Tested a modeline that is not pre-computed and able to see pixel clock calculation done correctly and the analyzer turns on: adjusted mode: "3440x1440": 50 265250 3440 3488 3520 3600 1440 1443 1453 1474 0x48 0x9 crtc timings: clock=265250, hd=3440 hb=3440-3600 hs=3488-3520 ht=3600, vd=1440 vb=1440-1474 vs=1443-1453 vt=1474, flags=0x9 Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com> On Mon, 2025-01-20 at 09:51 +0530, Ankit Nautiyal wrote: > The HDMI PLL programming involves pre-calculated values for specific > frequencies and an algorithm to compute values for other frequencies. > While the algorithm itself wasn't part of the driver, tables were > added based on it for known modes. > > Some HDMI modes were pruned due to lack of support (for example > issues > [1],[2], and [3]). > This series adds the algorithm for computing HDMI PLLs for > SNPS/C10PHY > to work with all modes supported by the hardware. > > The original algorithm uses floating-point math, which has been > converted to integers while preserving precision. As a result, > the values in the existing computable tables are very close but not > exact. Testing with DG2 and MTL on various panels revealed no issues. > > [1] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9722 > [2] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10654 > [3] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10956 > > Rev2: > -Change the name of the new file for HDMI PLL algorithm. > -Fix styling issues and bit refactoring for readbility. > -Fix issues reported by kernel test bot. > > Rev3: > -Modify the names of helper functions to align with filename. > > Rev4: > -Rebase, added Bspec references, and address review comments. > > Ankit Nautiyal (5): > drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for > DG2 > drm/i915/snps_phy: Use HDMI PLL algorithm for DG2 > drm/i915/cx0_phy_regs: Add C10 registers bits > drm/i915/intel_snps_hdmi_pll: Compute C10 HDMI PLLs with algorithm > drm/i915/cx0_phy: Use HDMI PLL algorithm for C10 PHY > > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 49 +-- > drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 - > .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 24 ++ > drivers/gpu/drm/i915/display/intel_hdmi.c | 12 - > .../drm/i915/display/intel_snps_hdmi_pll.c | 364 > ++++++++++++++++++ > .../drm/i915/display/intel_snps_hdmi_pll.h | 17 + > drivers/gpu/drm/i915/display/intel_snps_phy.c | 37 +- > drivers/gpu/drm/i915/display/intel_snps_phy.h | 1 - > drivers/gpu/drm/xe/Makefile | 1 + > 10 files changed, 427 insertions(+), 80 deletions(-) > create mode 100644 > drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c > create mode 100644 > drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h >
On 1/22/2025 4:15 AM, Almahallawy, Khaled wrote: > Thank You for the series. > Tested a modeline that is not pre-computed and able to see pixel clock > calculation done correctly and the analyzer turns on: > > adjusted mode: "3440x1440": 50 265250 3440 3488 3520 3600 1440 1443 > 1453 1474 0x48 0x9 > crtc timings: clock=265250, hd=3440 hb=3440-3600 hs=3488-3520 ht=3600, > vd=1440 vb=1440-1474 vs=1443-1453 vt=1474, flags=0x9 > > Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Thanks Khaled for the testing. Jani, does the series looks alright to merge? Regards, Ankit > > On Mon, 2025-01-20 at 09:51 +0530, Ankit Nautiyal wrote: >> The HDMI PLL programming involves pre-calculated values for specific >> frequencies and an algorithm to compute values for other frequencies. >> While the algorithm itself wasn't part of the driver, tables were >> added based on it for known modes. >> >> Some HDMI modes were pruned due to lack of support (for example >> issues >> [1],[2], and [3]). >> This series adds the algorithm for computing HDMI PLLs for >> SNPS/C10PHY >> to work with all modes supported by the hardware. >> >> The original algorithm uses floating-point math, which has been >> converted to integers while preserving precision. As a result, >> the values in the existing computable tables are very close but not >> exact. Testing with DG2 and MTL on various panels revealed no issues. >> >> [1] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9722 >> [2] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10654 >> [3] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10956 >> >> Rev2: >> -Change the name of the new file for HDMI PLL algorithm. >> -Fix styling issues and bit refactoring for readbility. >> -Fix issues reported by kernel test bot. >> >> Rev3: >> -Modify the names of helper functions to align with filename. >> >> Rev4: >> -Rebase, added Bspec references, and address review comments. >> >> Ankit Nautiyal (5): >> drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for >> DG2 >> drm/i915/snps_phy: Use HDMI PLL algorithm for DG2 >> drm/i915/cx0_phy_regs: Add C10 registers bits >> drm/i915/intel_snps_hdmi_pll: Compute C10 HDMI PLLs with algorithm >> drm/i915/cx0_phy: Use HDMI PLL algorithm for C10 PHY >> >> drivers/gpu/drm/i915/Makefile | 1 + >> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 49 +-- >> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 - >> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 24 ++ >> drivers/gpu/drm/i915/display/intel_hdmi.c | 12 - >> .../drm/i915/display/intel_snps_hdmi_pll.c | 364 >> ++++++++++++++++++ >> .../drm/i915/display/intel_snps_hdmi_pll.h | 17 + >> drivers/gpu/drm/i915/display/intel_snps_phy.c | 37 +- >> drivers/gpu/drm/i915/display/intel_snps_phy.h | 1 - >> drivers/gpu/drm/xe/Makefile | 1 + >> 10 files changed, 427 insertions(+), 80 deletions(-) >> create mode 100644 >> drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c >> create mode 100644 >> drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h >>
On Wed, 22 Jan 2025, "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com> wrote: > On 1/22/2025 4:15 AM, Almahallawy, Khaled wrote: >> Thank You for the series. >> Tested a modeline that is not pre-computed and able to see pixel clock >> calculation done correctly and the analyzer turns on: >> >> adjusted mode: "3440x1440": 50 265250 3440 3488 3520 3600 1440 1443 >> 1453 1474 0x48 0x9 >> crtc timings: clock=265250, hd=3440 hb=3440-3600 hs=3488-3520 ht=3600, >> vd=1440 vb=1440-1474 vs=1443-1453 vt=1474, flags=0x9 >> >> Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com> > > Thanks Khaled for the testing. > > Jani, does the series looks alright to merge? Acked-by: Jani Nikula <jani.nikula@intel.com> > > > Regards, > > Ankit > >> >> On Mon, 2025-01-20 at 09:51 +0530, Ankit Nautiyal wrote: >>> The HDMI PLL programming involves pre-calculated values for specific >>> frequencies and an algorithm to compute values for other frequencies. >>> While the algorithm itself wasn't part of the driver, tables were >>> added based on it for known modes. >>> >>> Some HDMI modes were pruned due to lack of support (for example >>> issues >>> [1],[2], and [3]). >>> This series adds the algorithm for computing HDMI PLLs for >>> SNPS/C10PHY >>> to work with all modes supported by the hardware. >>> >>> The original algorithm uses floating-point math, which has been >>> converted to integers while preserving precision. As a result, >>> the values in the existing computable tables are very close but not >>> exact. Testing with DG2 and MTL on various panels revealed no issues. >>> >>> [1] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9722 >>> [2] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10654 >>> [3] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10956 >>> >>> Rev2: >>> -Change the name of the new file for HDMI PLL algorithm. >>> -Fix styling issues and bit refactoring for readbility. >>> -Fix issues reported by kernel test bot. >>> >>> Rev3: >>> -Modify the names of helper functions to align with filename. >>> >>> Rev4: >>> -Rebase, added Bspec references, and address review comments. >>> >>> Ankit Nautiyal (5): >>> drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for >>> DG2 >>> drm/i915/snps_phy: Use HDMI PLL algorithm for DG2 >>> drm/i915/cx0_phy_regs: Add C10 registers bits >>> drm/i915/intel_snps_hdmi_pll: Compute C10 HDMI PLLs with algorithm >>> drm/i915/cx0_phy: Use HDMI PLL algorithm for C10 PHY >>> >>> drivers/gpu/drm/i915/Makefile | 1 + >>> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 49 +-- >>> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 - >>> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 24 ++ >>> drivers/gpu/drm/i915/display/intel_hdmi.c | 12 - >>> .../drm/i915/display/intel_snps_hdmi_pll.c | 364 >>> ++++++++++++++++++ >>> .../drm/i915/display/intel_snps_hdmi_pll.h | 17 + >>> drivers/gpu/drm/i915/display/intel_snps_phy.c | 37 +- >>> drivers/gpu/drm/i915/display/intel_snps_phy.h | 1 - >>> drivers/gpu/drm/xe/Makefile | 1 + >>> 10 files changed, 427 insertions(+), 80 deletions(-) >>> create mode 100644 >>> drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c >>> create mode 100644 >>> drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h >>>
Hi, The below failure is not related to the patch series. The test was passing in previous revision v4: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v4/bat-adlp-9/igt@i915_selftest@live.html The v5 is just a minor change in macro in patch#2, sent in-reply-to it, so both versions are practically same. Therefore, went ahead and merged the series since BAT and CI are already clean for v4. Regards, Ankit On 1/22/2025 11:20 PM, Patchwork wrote: > Project List - Patchwork *Patch Details* > *Series:* Add HDMI PLL Algorithm for SNPS/C10PHY (rev5) > *URL:* https://patchwork.freedesktop.org/series/135397/ > *State:* failure > *Details:* > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/index.html > > > CI Bug Log - changes from CI_DRM_16001 -> Patchwork_135397v5 > > > Summary > > *FAILURE* > > Serious unknown changes coming with Patchwork_135397v5 absolutely need > to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_135397v5, please notify your bug team > (I915-ci-infra@lists.freedesktop.org) to allow them > to document this new failure mode, which will reduce false positives > in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/index.html > > > Participating hosts (45 -> 44) > > Missing (1): fi-snb-2520m > > > Possible new issues > > Here are the unknown changes that may have been introduced in > Patchwork_135397v5: > > > IGT changes > > > Possible regressions > > * igt@i915_selftest@live: > o bat-adlp-9: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-adlp-9/igt@i915_selftest@live.html> > -> ABORT > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-adlp-9/igt@i915_selftest@live.html> > > > Known issues > > Here are the changes found in Patchwork_135397v5 that come from known > issues: > > > IGT changes > > > Issues hit > > * > > igt@dmabuf@all-tests: > > o bat-apl-1: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-apl-1/igt@dmabuf@all-tests.html> > -> INCOMPLETE > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-apl-1/igt@dmabuf@all-tests.html> > (i915#12904 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904>) > +1 other test incomplete > * > > igt@gem_lmem_swapping@verify-random: > > o fi-cfl-8109u: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/fi-cfl-8109u/igt@gem_lmem_swapping@verify-random.html> > (i915#4613 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613>) > +3 other tests skip > * > > igt@i915_module_load@load: > > o fi-pnv-d510: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/fi-pnv-d510/igt@i915_module_load@load.html> > -> ABORT > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/fi-pnv-d510/igt@i915_module_load@load.html> > (i915#13203 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13203>) > * > > igt@i915_pm_rpm@module-reload: > > o bat-dg2-11: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-dg2-11/igt@i915_pm_rpm@module-reload.html> > -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-dg2-11/igt@i915_pm_rpm@module-reload.html> > (i915#13401 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13401>) > o bat-dg1-7: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-dg1-7/igt@i915_pm_rpm@module-reload.html> > -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-dg1-7/igt@i915_pm_rpm@module-reload.html> > (i915#13401 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13401>) > * > > igt@i915_selftest@live: > > o bat-arlh-3: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-arlh-3/igt@i915_selftest@live.html> > -> DMESG-FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-arlh-3/igt@i915_selftest@live.html> > (i915#12061 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061> > / i915#12435 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12435>) > * > > igt@i915_selftest@live@gt_mocs: > > o bat-adlp-9: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-adlp-9/igt@i915_selftest@live@gt_mocs.html> > -> ABORT > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-adlp-9/igt@i915_selftest@live@gt_mocs.html> > (i915#13399 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13399>) > * > > igt@i915_selftest@live@workarounds: > > o bat-arlh-3: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-arlh-3/igt@i915_selftest@live@workarounds.html> > -> DMESG-FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-arlh-3/igt@i915_selftest@live@workarounds.html> > (i915#12061 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061>) > * > > igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: > > o bat-dg2-11: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html> > -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html> > (i915#9197 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197>) > +3 other tests skip > > > Possible fixes > > * > > igt@i915_module_load@reload: > > o fi-cfl-8109u: ABORT > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/fi-cfl-8109u/igt@i915_module_load@reload.html> > -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/fi-cfl-8109u/igt@i915_module_load@reload.html> > * > > igt@i915_pm_rpm@module-reload: > > o bat-dg2-9: ABORT > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-dg2-9/igt@i915_pm_rpm@module-reload.html> > -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-dg2-9/igt@i915_pm_rpm@module-reload.html> > * > > igt@kms_force_connector_basic@prune-stale-modes: > > o bat-dg2-13: SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-dg2-13/igt@kms_force_connector_basic@prune-stale-modes.html> > (i915#5274 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274>) > -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-dg2-13/igt@kms_force_connector_basic@prune-stale-modes.html> > o bat-dg2-9: SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-dg2-9/igt@kms_force_connector_basic@prune-stale-modes.html> > (i915#5274 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274>) > -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-dg2-9/igt@kms_force_connector_basic@prune-stale-modes.html> > o bat-mtlp-6: SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-mtlp-6/igt@kms_force_connector_basic@prune-stale-modes.html> > (i915#5274 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274> > / i915#9792 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9792>) > -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-mtlp-6/igt@kms_force_connector_basic@prune-stale-modes.html> > o bat-dg2-14: SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-dg2-14/igt@kms_force_connector_basic@prune-stale-modes.html> > (i915#5274 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274>) > -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-dg2-14/igt@kms_force_connector_basic@prune-stale-modes.html> > o bat-dg2-11: SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-dg2-11/igt@kms_force_connector_basic@prune-stale-modes.html> > (i915#5274 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274>) > -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-dg2-11/igt@kms_force_connector_basic@prune-stale-modes.html> > o bat-mtlp-8: SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html> > (i915#5274 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274>) > -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html> > o bat-dg2-8: SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-dg2-8/igt@kms_force_connector_basic@prune-stale-modes.html> > (i915#5274 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274>) > -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-dg2-8/igt@kms_force_connector_basic@prune-stale-modes.html> > o {bat-mtlp-9}: SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-mtlp-9/igt@kms_force_connector_basic@prune-stale-modes.html> > (i915#5274 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274>) > -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-mtlp-9/igt@kms_force_connector_basic@prune-stale-modes.html> > o bat-arlh-3: SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16001/bat-arlh-3/igt@kms_force_connector_basic@prune-stale-modes.html> > (i915#12648 > <https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12648>) > -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_135397v5/bat-arlh-3/igt@kms_force_connector_basic@prune-stale-modes.html> > > {name}: This element is suppressed. This means it is ignored when > computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > > Build changes > > * Linux: CI_DRM_16001 -> Patchwork_135397v5 > > CI-20190529: 20190529 > CI_DRM_16001: 6834acba715b85cbecfeb660b9695806e98c9a0a @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_8206: 48d7780a026179e5de232142df3ac59fec6487ee @ > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_135397v5: 6834acba715b85cbecfeb660b9695806e98c9a0a @ > git://anongit.freedesktop.org/gfx-ci/linux >
On 1/22/2025 10:22 PM, Jani Nikula wrote: > On Wed, 22 Jan 2025, "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com> wrote: >> On 1/22/2025 4:15 AM, Almahallawy, Khaled wrote: >>> Thank You for the series. >>> Tested a modeline that is not pre-computed and able to see pixel clock >>> calculation done correctly and the analyzer turns on: >>> >>> adjusted mode: "3440x1440": 50 265250 3440 3488 3520 3600 1440 1443 >>> 1453 1474 0x48 0x9 >>> crtc timings: clock=265250, hd=3440 hb=3440-3600 hs=3488-3520 ht=3600, >>> vd=1440 vb=1440-1474 vs=1443-1453 vt=1474, flags=0x9 >>> >>> Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com> >> Thanks Khaled for the testing. >> >> Jani, does the series looks alright to merge? > Acked-by: Jani Nikula <jani.nikula@intel.com> Thanks Jani, Suraj and Khaled. This is now pushed to drm-intel-next. Regards, Ankit > > >> >> Regards, >> >> Ankit >> >>> On Mon, 2025-01-20 at 09:51 +0530, Ankit Nautiyal wrote: >>>> The HDMI PLL programming involves pre-calculated values for specific >>>> frequencies and an algorithm to compute values for other frequencies. >>>> While the algorithm itself wasn't part of the driver, tables were >>>> added based on it for known modes. >>>> >>>> Some HDMI modes were pruned due to lack of support (for example >>>> issues >>>> [1],[2], and [3]). >>>> This series adds the algorithm for computing HDMI PLLs for >>>> SNPS/C10PHY >>>> to work with all modes supported by the hardware. >>>> >>>> The original algorithm uses floating-point math, which has been >>>> converted to integers while preserving precision. As a result, >>>> the values in the existing computable tables are very close but not >>>> exact. Testing with DG2 and MTL on various panels revealed no issues. >>>> >>>> [1] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9722 >>>> [2] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10654 >>>> [3] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10956 >>>> >>>> Rev2: >>>> -Change the name of the new file for HDMI PLL algorithm. >>>> -Fix styling issues and bit refactoring for readbility. >>>> -Fix issues reported by kernel test bot. >>>> >>>> Rev3: >>>> -Modify the names of helper functions to align with filename. >>>> >>>> Rev4: >>>> -Rebase, added Bspec references, and address review comments. >>>> >>>> Ankit Nautiyal (5): >>>> drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for >>>> DG2 >>>> drm/i915/snps_phy: Use HDMI PLL algorithm for DG2 >>>> drm/i915/cx0_phy_regs: Add C10 registers bits >>>> drm/i915/intel_snps_hdmi_pll: Compute C10 HDMI PLLs with algorithm >>>> drm/i915/cx0_phy: Use HDMI PLL algorithm for C10 PHY >>>> >>>> drivers/gpu/drm/i915/Makefile | 1 + >>>> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 49 +-- >>>> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 - >>>> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 24 ++ >>>> drivers/gpu/drm/i915/display/intel_hdmi.c | 12 - >>>> .../drm/i915/display/intel_snps_hdmi_pll.c | 364 >>>> ++++++++++++++++++ >>>> .../drm/i915/display/intel_snps_hdmi_pll.h | 17 + >>>> drivers/gpu/drm/i915/display/intel_snps_phy.c | 37 +- >>>> drivers/gpu/drm/i915/display/intel_snps_phy.h | 1 - >>>> drivers/gpu/drm/xe/Makefile | 1 + >>>> 10 files changed, 427 insertions(+), 80 deletions(-) >>>> create mode 100644 >>>> drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c >>>> create mode 100644 >>>> drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h >>>>