From patchwork Mon Jan 27 10:28:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13951194 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2DF07C02188 for ; Mon, 27 Jan 2025 10:29:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A122210E236; Mon, 27 Jan 2025 10:29:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="SFN66ecn"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0144210E236; Mon, 27 Jan 2025 10:29:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737973746; x=1769509746; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=dpn3c+Xrgvy2J5EkiL0y2rL4H9yV5/C6V0MmgldxYnA=; b=SFN66ecnb6BA1+1wymJhv6j6AgJPXvWBHr9kkgkilfq1vjyc8vRQ77+J DziVNq1RQG/mSCuIPEqwcPH/q83xv7YlsOWiECGkjRFnWXJ42oIDRIPli Ls20hG4tM9g/VgxZlh7zoRV9V7DJWcw+01/D2SUM23v4essIdfs9nNBWR VrrBoTn6bdov0yQPANZlowrUE1gnS7fHan48AGWaMXbRTTcb5HpfKPS9i R8Rllmxc6O94C+a+bIQMqKPFC59tBZ9hqaYHdINmUlL5HCfFgjf5XMFtr 4fL2x7n4v+qidvOSOz+39S42VpjSbFuCwDCVbHVQ7HhMeJ4PIVOpkOGnK A==; X-CSE-ConnectionGUID: l4gyjdt0TMaBRg64bdRiIA== X-CSE-MsgGUID: 1ag9VVgoRNOhIhd8RgbmAw== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="38529849" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="38529849" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jan 2025 02:29:05 -0800 X-CSE-ConnectionGUID: UmUGi6bZR8Gism/RA7dy1A== X-CSE-MsgGUID: uhb8o5GoQiOzC6/jLD2d5w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="108837774" Received: from mjarzebo-mobl1.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.244.95]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jan 2025 02:29:03 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: animesh.manna@intel.com, ville.syrjala@intel.com, =?utf-8?q?Jouni_H?= =?utf-8?q?=C3=B6gander?= Subject: [PATCH v6 00/12] PSR DSB support Date: Mon, 27 Jan 2025 12:28:34 +0200 Message-ID: <20250127102846.1237560-1-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This patch set is doing necessary modifications to support PSR update using DSB on LunarLake onwards It is not necessary to wait for PSR1 to idle or PSR2 to exit DEEP sleep at the begin of commit This is left out from DSB commit. There might be room for optimization for non-DSB as well because such wait is not supposed to be necessary at the begin of update. PSR mutex is not locked when performing DSB commit. It is not necessary as we are currently using DSB only when sending updates towards panel. I.e. not using it when changing PSR mode. Also necessary changes are made to use PSR2_MAN_TRK_CTL only in DSB. Frontbuffer updates and legacy cursor updates are using SFF_CTL register to perform full frame updates. DSB_SKIP_WAITS_EN is removed to ensure all waits are performed when PSR is active. PSR "Frame Change" event is manually triggered at the begin of each DSB commit by adding CURSURFLIVE register write. Possibe problem with DSB commit when PSR is already waking up is avoided by evading scanline 0. v6: - add comment explaining why we are not setting DSB_SKIP_WAITS_EN - add separate function to generate the "Frame change"evant. - use intel_dsb_emit_wait_dsl - add evasion of scanline 0 also for Panel Replay v5: - rebase v4: - remove DSB_SKIP_WAITS_EN - Add CURSURFLIVE register write at the begin of DSB commit - evade scanline 0 v3: - do not use DSB when PSR mode is changing v2: - use _MMIO_TRANS instead of _MMIO_TRANS2 - drop evasion from intel_psr_configure_full_frame_update Jouni Högander (12): drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update drm/i915/psr: Rename psr_force_hw_tracking_exit as intel_psr_force_update drm/i915/psr: Split setting sff and cff bits away from intel_psr_force_update drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL registers drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards drm/i915/psr: Allow writing PSR2_MAN_TRK_CTL using DSB drm/i915/psr: Changes for PSR2_MAN_TRK_CTL handling when DSB is in use drm/i915/psr: Remove DSB_SKIP_WAITS_EN chicken bit drm/i915/display: Evade scanline 0 as well if PSR1 or PSR2 is enabled drm/i915/psr: Add function for triggering "Frame Change" event drm/i915/display: Ensure we have "Frame Change" event in DSB commit drm/i915/psr: Allow DSB usage when PSR is enabled drivers/gpu/drm/i915/display/intel_display.c | 16 +- drivers/gpu/drm/i915/display/intel_dsb.c | 27 +++- drivers/gpu/drm/i915/display/intel_psr.c | 141 +++++++++--------- drivers/gpu/drm/i915/display/intel_psr.h | 7 +- drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 ++ 5 files changed, 128 insertions(+), 73 deletions(-)