From patchwork Mon Apr 7 08:16:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 14039952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A865C36010 for ; Mon, 7 Apr 2025 08:16:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 11E3510E3A2; Mon, 7 Apr 2025 08:16:50 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="dPamiwYY"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0B31A10E39E; Mon, 7 Apr 2025 08:16:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744013808; x=1775549808; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=p1G/PPz9oj42/wY/TpCKypA7pafTszpqXL5Z+1x0gmY=; b=dPamiwYY4MIM+Po2sQMwfTjx4cBOmDghBaRsjKIr1jxJR9aZRR1PJueN juR9JIAC/BdUkRSEnpHlUbmfSra7YHDWt6iW2vLt9eZDDKmwILpwQod1d L9UDGEqV+NrE/bc1jTVmO+t0wIpgB2nt+ogRc4XQw9GOvqtcDKR1U2GtL 2vaQS62sha6x+eg4B454xgB4UmZf2jedPGJ2feXgfg//i7SsXRbOQlkAL ju7AzxVs1dxOoXKFGP1whGjhvavLZ3jcWB8FQZ4Qz4EvYlFEYlxuYEvPY ZIc1Zq3r8sIPpyrBYxNnn1wnOGwQ4n41kH6NlrWRkBQFYLmOXuX28/E3P A==; X-CSE-ConnectionGUID: obltnMFNTMy9r1IKZgZYZQ== X-CSE-MsgGUID: k3CnsQc7Q6eH+oEEo+wHXA== X-IronPort-AV: E=McAfee;i="6700,10204,11396"; a="56755736" X-IronPort-AV: E=Sophos;i="6.15,193,1739865600"; d="scan'208";a="56755736" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2025 01:16:48 -0700 X-CSE-ConnectionGUID: G/a0RrHvSkGZEs4xb97nTw== X-CSE-MsgGUID: 5OhqKS7FTwKHgxJo+t21wQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,193,1739865600"; d="scan'208";a="127727895" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa006.fm.intel.com with ESMTP; 07 Apr 2025 01:16:45 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, jani.nikula@intel.com, mika.kahola@intel.com, ville.syrjala@intel.com, Suraj Kandpal Subject: [PATCH 00/18] DPLL framework redesign Date: Mon, 7 Apr 2025 13:46:36 +0530 Message-Id: <20250407081654.2013680-1-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Since MTL we moved away from using our existing DPLL framework this was done since the existing API didnt really work for us. This Redesing is a first part of two part series which will redesign the current framework so that it can be used for PLL/PHY enablement going forward. Here we move away from the shared_dpll naming and also change arguments for some functions which are needed for PLL which have individual PHY keeping in mind that we don't break any of the legacy stuff. When this gets approved and merged a second series hooking up the SNPS PHY PLL API to this framework will be posted. This is done to reduce the rework in case the current design floated ends up getting changed during the review process. We also rename some functions in intel_dpll_mgr to start with intel_dpll_* in an effort to make sure all exported functions have the filename at the start. Signed-off-by: Suraj Kandpal Suraj Kandpal (18): drm/i915/dpll: Rename intel_dpll drm/i915/dpll: Rename intel_dpll_funcs drm/i915/dpll: Rename intel_shared_dpll_state drm/i915/dpll: Rename macro for_each_shared_dpll drm/i915/dpll: Rename intel_shared_dpll_funcs drm/i915/dpll: Rename intel_shared_dpll drm/i915/dpll: Move away from using shared dpll drm/i915/dpll: Rename crtc_get_shared_dpll drm/i915/dpll: Change argument for enable hook in intel_dpll_funcs drm/i915/drm: Rename disable hook in intel_dpll_global_func drm/i915/dpll: Introduce new hook in intel_dpll_funcs drm/i915/dpll: Add intel_encoder argument to get_hw_state hook drm/i915/dpll: Change arguments for get_freq hook drm/i915/dpll: Rename intel_[enable/disable]_dpll drm/i915/dpll: Rename intel_unreference_dpll__crtc drm/i915/dpll: Rename intel__dpll drm/i915/dpll: Rename intel_compute_dpll drm/i915/dpll: Rename intel_update_active_dpll drivers/gpu/drm/i915/display/icl_dsi.c | 2 +- drivers/gpu/drm/i915/display/intel_ddi.c | 70 +- drivers/gpu/drm/i915/display/intel_ddi.h | 6 +- drivers/gpu/drm/i915/display/intel_display.c | 22 +- .../gpu/drm/i915/display/intel_display_core.h | 12 +- .../drm/i915/display/intel_display_debugfs.c | 4 +- .../drm/i915/display/intel_display_driver.c | 2 +- .../drm/i915/display/intel_display_types.h | 8 +- drivers/gpu/drm/i915/display/intel_dpll.c | 60 +- drivers/gpu/drm/i915/display/intel_dpll.h | 4 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 768 +++++++++--------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 83 +- drivers/gpu/drm/i915/display/intel_fdi.c | 2 +- drivers/gpu/drm/i915/display/intel_lvds.c | 2 +- .../drm/i915/display/intel_modeset_setup.c | 10 +- .../drm/i915/display/intel_modeset_verify.c | 4 +- .../gpu/drm/i915/display/intel_pch_display.c | 20 +- .../gpu/drm/i915/display/intel_pch_refclk.c | 4 +- 18 files changed, 552 insertions(+), 531 deletions(-)