Show patches with: State = Action Required       |   123529 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[07/15] drm/i915/gtt: call chipset flush directly - - - --- 2010-11-06 Daniel Vetter New
[06/15] drm/i915|intel-gtt: consolidate intel-gtt.h headers - - - --- 2010-11-06 Daniel Vetter New
[05/15] intel-gtt: fold i81x-only dcache support into the generic driver - - - --- 2010-11-06 Daniel Vetter New
[04/15] intel-gtt: switch i81x to the common initialization helpers - - - --- 2010-11-06 Daniel Vetter New
[03/15] intel-gtt: switch i81x to the write_entry helpers - - - --- 2010-11-06 Daniel Vetter New
[02/15] intel-gtt: kill unneeded sandybridge memory types - - - --- 2010-11-06 Daniel Vetter New
[01/15] intel-gtt: drop dcache support for i830 and later - - - --- 2010-11-06 Daniel Vetter New
intel: Fix emit_linear_blit to use DWORD aligned width blits - - - --- 2010-11-06 Peter Clifton New
intel: Fix emit_linear_blit to use DWORD aligned width blits - - - --- 2010-11-06 Peter Clifton New
i915_gem_evict_something in sysprof trace using VBOs - - - --- 2010-11-05 Peter Clifton New
[bisected] commit 176f28eb breaks my Sandybridge - - - --- 2010-11-04 Carl Worth New
[2/2] agp/intel: restore cache behavior on sandybridge - - - --- 2010-11-02 Zhenyu Wang New
[1/2] agp/intel: fix cache control for sandybridge - - - --- 2010-11-02 Zhenyu Wang New
drm/i915: Add aub debug support for kernel - - - --- 2010-11-02 Yuanhan Liu New
drm/i915: SNB BLT workaround - - - --- 2010-11-02 Zou, Nanhai New
drm/i915: Fix the graphics frequency clamping at init and when IPS is active. - - - --- 2010-11-01 Eric Anholt New
drm/i915: remove debug fmax - - - --- 2010-11-01 Jesse Barnes New
[4/4] cpuidle: Hack iowait weighting to avoid C-state reduction for graphics. - - - --- 2010-11-01 Eric Anholt New
[3/4] drm/i915: Declare waits on GPU as io waits, to reduce C-state reduction. - - - --- 2010-11-01 Eric Anholt New
[2/4] Add io_ variants of wait_event() and wait_event_interruptible() - - - --- 2010-11-01 Eric Anholt New
[1/4] sched: Export io_schedule_timeout() - - - --- 2010-11-01 Eric Anholt New
drm/i915: I915_WRITE16 should call writew - - - --- 2010-11-01 Yuanhan Liu New
[5/5] render: use headerless render target write - - - --- 2010-11-01 Xiang, Haihao New
[4/5] render: acceleration for composite on Sandybridge - - - --- 2010-11-01 Xiang, Haihao New
[3/5] render: fragments for composite on Sandybridge - - - --- 2010-11-01 Xiang, Haihao New
[2/5] render: fix send instruction used in sampling fragments - - - --- 2010-11-01 Xiang, Haihao New
[1/5] render: set the surface state base address - - - --- 2010-11-01 Xiang, Haihao New
[2/2] support BLT acceleration on gen6 - - - --- 2010-11-01 Zou, Nanhai New
[1/2] add BLT ring support - - - --- 2010-11-01 Zou, Nanhai New
INSTDONE instrumentation (patch in progress) - - - --- 2010-10-31 Peter Clifton New
enable BLT acceleate on gen6 - - - --- 2010-10-29 Zou, Nanhai New
drm/i915: Fix KMS regression on Sandybridge/CPT - - - --- 2010-10-28 Zhenyu Wang New
[v2] drm/i915: set scanout buffer as uncached on Sandybridge - - - --- 2010-10-28 Zhenyu Wang New
enable blt acceleration on gen6 - - - --- 2010-10-27 Zou, Nanhai New
[PATH,v2,6/6] Xv: don't call intel_wait_for_scanline on Sandybridge - - - --- 2010-10-27 Xiang, Haihao New
[PATH,v2,5/6] Xv: enable TextureAdaptor for Sandybridge - - - --- 2010-10-27 Xiang, Haihao New
[PATH,v2,4/6] Xv: setup pipeline for Xv on Sandybridge - - - --- 2010-10-27 Xiang, Haihao New
[PATH,v2,3/6] Xv: fragments for xv on Sandybridge. - - - --- 2010-10-27 Xiang, Haihao New
[PATH,v2,2/6] Xv: Send instruction doesn't use implied move when sampling YUV surface - - - --- 2010-10-27 Xiang, Haihao New
[PATH,v2,1/6] Xv: set the surface state base address - - - --- 2010-10-27 Xiang, Haihao New
[2/2] use BLT command to accelerate uxa on gen6. - - - --- 2010-10-26 Zou, Nanhai New
[1/2] split render engine batch buffer and BLT engine - - - --- 2010-10-26 Zou, Nanhai New
drm/i915: set scan-buffer as uncached on Sandybridge - - - --- 2010-10-25 Zhenyu Wang New
Corruption in glxgears with Compiz - - - --- 2010-10-23 Chris Wilson New
Corruption in glxgears with Compiz - - - --- 2010-10-23 Peter Clifton New
Corruption in glxgears with Compiz - - - --- 2010-10-23 Peter Clifton New
Chris Wilson <chris@chris-wilson.co.uk> - - - --- 2010-10-22 Peter Clifton New
drm/i915: Fix current fb blocking for page flip. - - - --- 2010-10-21 Chia-I Wu New
drm/i915: fix current fb blocking for flipping. - - - --- 2010-10-21 Chia-I Wu New
[6/6] Xv: don't call intel_wait_for_scanline on Sandybridge - - - --- 2010-10-21 Xiang, Haihao New
[5/6] Xv: enable TextureAdaptor for Sandybridge - - - --- 2010-10-21 Xiang, Haihao New
[4/6] Xv: setup pipeline for Xv on Sandybridge - - - --- 2010-10-21 Xiang, Haihao New
[3/6] Xv: fragments for xv on Sandybridge. - - - --- 2010-10-21 Xiang, Haihao New
[2/6] Xv: Send instruction doesn't use implied move when sampling YUV surface - - - --- 2010-10-21 Xiang, Haihao New
[1/6] Xv: set the surface state base address - - - --- 2010-10-21 Xiang, Haihao New
[-next,2/2] drm/i915: Fix GPIO pin to register mapping - - - --- 2010-10-13 Zhenyu Wang New
[-next,1/2] drm/i915: restore FDI link rate on sandybridge - - - --- 2010-10-13 Zhenyu Wang New
Strange performance cliff... - - - --- 2010-10-12 Peter Clifton New
intel: new blitter ring support from Sandybridge - - - --- 2010-10-12 Zhenyu Wang New
drm/i915: new blitter ring support from Sandybridge - - - --- 2010-10-12 Zhenyu Wang New
[10/10] no compression flag on Sandybridge - - - --- 2010-10-09 Xiang, Haihao New
[09/10] print error message when using math function on Sandybridge. - - - --- 2010-10-09 Xiang, Haihao New
[08/10] sampler, urb write, null and gateway on Sandybridge are same as Ironlake. - - - --- 2010-10-09 Xiang, Haihao New
[07/10] add support for data port read on Sandybridge - - - --- 2010-10-09 Xiang, Haihao New
[06/10] add support for data port write on Sandybridge. - - - --- 2010-10-09 Xiang, Haihao New
[05/10] fix send instruction on Sandybridge - - - --- 2010-10-09 Xiang, Haihao New
[04/10] add AccWrCtrl flag on Sandybridge - - - --- 2010-10-09 Xiang, Haihao New
[03/10] always set destination horiz stride for Align16 to 1 on Sandybridge. - - - --- 2010-10-09 Xiang, Haihao New
[02/10] fix jump count for Sandybridge. - - - --- 2010-10-09 Xiang, Haihao New
[01/10] add -g 6 for Sandybridge - - - --- 2010-10-09 Xiang, Haihao New
drm/i915/dp: down the DP link even if the reg indicates it's already down - - - --- 2010-10-08 Jesse Barnes New
Make driver compile for 1.6 Xserver series again. Part deux. - - - --- 2010-10-08 Matthias Hopf New
drm/i915: Prevent module unload to avoid random memory corruption - - - --- 2010-10-08 Chris Wilson New
drm/i915: make sure hotpulg is enabled - - - --- 2010-10-08 Yuanhan Liu New
i915: Initialize panel timing registers if VBIOS did not. - - - --- 2010-10-08 Bryan Freed New
[20/20] drm/i915: diasable clock gating for the panel power sequencer - - - --- 2010-10-07 Jesse Barnes New
[19/20] drm/i915/dp: make eDP PLL functions work as advertised - - - --- 2010-10-07 Jesse Barnes New
[18/20] drm/i915/dp: don't bother with DP PLL for PCH attached eDP - - - --- 2010-10-07 Jesse Barnes New
[17/20] drm/i915/dp: use VBT provided eDP params if available - - - --- 2010-10-07 Jesse Barnes New
[16/20] drm/i915/dp: cache eDP DPCD data - - - --- 2010-10-07 Jesse Barnes New
[15/20] drm/i915: don't program FDI RX/TX in mode_set - - - --- 2010-10-07 Jesse Barnes New
[14/20] drm/i915: fix ironlake CRTC enable/disable - - - --- 2010-10-07 Jesse Barnes New
[13/20] drm/i915: use DPLL_DVO_HIGH_SPEED for PCH eDP - - - --- 2010-10-07 Jesse Barnes New
[12/20] drm/i915: use 120MHz refclk in PCH eDP case too - - - --- 2010-10-07 Jesse Barnes New
[11/20] drm/i915: fix PCH eDP SSC support - - - --- 2010-10-07 Jesse Barnes New
[10/20] drm/i915: add Ironlake clock gating workaround for FDI link training - - - --- 2010-10-07 Jesse Barnes New
[09/20] drm/i915: fetch eDP configuration data from the VBT - - - --- 2010-10-07 Jesse Barnes New
[08/20] drm/i915: add _DSM support - - - --- 2010-10-07 Jesse Barnes New
[07/20] drm/i915/dp: eDP power sequencing fixes - - - --- 2010-10-07 Jesse Barnes New
[06/20] drm/i915: fix CPU vs PCH eDP confusion - - - --- 2010-10-07 Jesse Barnes New
[05/20] drm/i915: remove broken intel_pch_has_edp function - - - --- 2010-10-07 Jesse Barnes New
[04/20] drm/i915: add eDP checking functions for the display code - - - --- 2010-10-07 Jesse Barnes New
[03/20] drm/i915/dp: correct eDP lane count and bpp - - - --- 2010-10-07 Jesse Barnes New
[02/20] drm/i915/dp: remove redundant is_pch_edp checks - - - --- 2010-10-07 Jesse Barnes New
[01/20] drm/i915/dp: convert eDP checks to functions and document - - - --- 2010-10-07 Jesse Barnes New
CHROMIUM: i915: Initialize panel timing registers if VBIOS did not. - - - --- 2010-10-07 Bryan Freed New
H55 chipset and KMS with HDMI/VGA - - - --- 2010-10-07 Chris Wilson New
drm/i915: Free hardware status page on unload when physically mapped - - - --- 2010-10-07 Keith Packard New
allow 945 to control self refresh automatically - - - --- 2010-10-04 Alexander Lam New
intel: Listen for hotplug uevents (V3) - - - --- 2010-10-04 Keith Packard New
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