Show patches with: Series = [CI,1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines       |   2 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[CI,2/2] drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLL [CI,1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider va… - 1 - --- 2018-08-17 Zanoni, Paulo R New
[CI,1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider va… [CI,1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider va… - 2 - --- 2018-08-17 Zanoni, Paulo R New