From patchwork Wed Apr 6 06:59:37 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 689301 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3670ILw003928 for ; Wed, 6 Apr 2011 07:00:39 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 290869E831 for ; Wed, 6 Apr 2011 00:00:18 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id B69969E74B for ; Tue, 5 Apr 2011 23:59:40 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 05 Apr 2011 23:59:40 -0700 Message-Id: <0d30dc$lntgob@orsmga001.jf.intel.com> X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.63,309,1299484800"; d="scan'208";a="729727755" Received: from unknown (HELO cwilso3-mobl.ger.corp.intel.com) ([10.255.16.165]) by orsmga001.jf.intel.com with SMTP; 05 Apr 2011 23:59:38 -0700 Received: by cwilso3-mobl.ger.corp.intel.com (sSMTP sendmail emulation); Wed, 06 Apr 2011 07:59:37 +0100 Date: Wed, 06 Apr 2011 07:59:37 +0100 To: Keith Packard , intel-gfx@lists.freedesktop.org References: <1301995458-2699-1-git-send-email-chris@chris-wilson.co.uk> <1301995458-2699-2-git-send-email-chris@chris-wilson.co.uk> From: Chris Wilson In-Reply-To: Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915: Initialise g4x watermarks for disabled pipes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 06 Apr 2011 07:00:39 +0000 (UTC) On Tue, 05 Apr 2011 18:02:51 -0700, Keith Packard wrote: > On Tue, 05 Apr 2011 22:12:19 +0100, Chris Wilson wrote: > > > Indeed, I started by setting them to zero in the caller. Decided that > > there was some precedent to use the guard_size as the minimum value for > > unused planes (and so perhaps the unused planes on the unused pipes) and > > so it was then natural to do it inside g4x_compute_wm. I guess it all > > depends on how many FIFOs are split between the pipes. Using guard_size, > > I believe, should be safest. > > guard_size is probably better than random stack stuff. Any opinion on > whether this should be done in g4x_update_wm instead of g4x_compute_wm0? I'd prefer to keep the mucking around with intel_watermak_params in the one spot. How about: diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f1798f2..dbe11eb 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3799,11 +3799,14 @@ static bool g4x_compute_wm0(struct drm_device *dev, int line_time_us, line_count; int entries, tlb_miss; + /* The FIFO requires a minimum number of entries (the guard size) + * as it switches between planes: + */ + *cursor_wm = cursor->guard_size; + *plane_wm = display->guard_size; + crtc = intel_get_crtc_for_plane(dev, plane); - if (crtc->fb == NULL || !crtc->enabled) { - *cursor_wm = *plane_wm = display->guard_size; + if (crtc->fb == NULL || !crtc->enabled) return false; - } htotal = crtc->mode.htotal; hdisplay = crtc->mode.hdisplay; @@ -3816,7 +3819,7 @@ static bool g4x_compute_wm0(struct drm_device *dev, if (tlb_miss > 0) entries += tlb_miss; entries = DIV_ROUND_UP(entries, display->cacheline_size); - *plane_wm = entries + display->guard_size; + *plane_wm += entries; if (*plane_wm > (int)display->max_wm) *plane_wm = display->max_wm; @@ -3828,7 +3831,7 @@ static bool g4x_compute_wm0(struct drm_device *dev, if (tlb_miss > 0) entries += tlb_miss; entries = DIV_ROUND_UP(entries, cursor->cacheline_size); - *cursor_wm = entries + cursor->guard_size; + *cursor_wm += entries; if (*cursor_wm > (int)cursor->max_wm) *cursor_wm = (int)cursor->max_wm;