From patchwork Wed Jul 22 09:34:57 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ling.ma@intel.com X-Patchwork-Id: 36736 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n6M9Z38H017427 for ; Wed, 22 Jul 2009 09:35:03 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2031E9F389; Wed, 22 Jul 2009 02:35:03 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id CF8629E885 for ; Wed, 22 Jul 2009 02:35:00 -0700 (PDT) Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga101.ch.intel.com with ESMTP; 22 Jul 2009 02:35:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.43,245,1246863600"; d="scan'208";a="167658178" Received: from unknown (HELO localhost.localdomain) ([10.239.36.100]) by azsmga001.ch.intel.com with ESMTP; 22 Jul 2009 02:34:59 -0700 From: ling.ma@intel.com To: eric@anholt.net Date: Wed, 22 Jul 2009 17:34:57 +0800 Message-Id: <1248255297-3275-1-git-send-email-ling.ma@intel.com> X-Mailer: git-send-email 1.5.4.4 Cc: Ma Ling , intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH V2] drm/i915: Disable VGA plane reliably X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.9 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org VGA random hang on recent G45/43 board. From spec, SR01 bit 5 should be set before VGA plane disable through control register, otherwise we might get random crash and lockups. sync up with 2D driver which fixed freedesktop.org bug #17235 Signed-off-by: Ma Ling --- clean up work in this version drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++++++++++++++++++++- 2 files changed, 30 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 897a116..563e01c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1767,6 +1767,7 @@ # define VGA_DISP_DISABLE (1 << 31) # define VGA_2X_MODE (1 << 30) # define VGA_PIPE_B_SELECT (1 << 29) +# define VGA_CENTER_ENABLE (3 << 24) /* IGDNG */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a58bfad..a10a303 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1281,6 +1281,34 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode) } } +static void +intel_crtc_disable_vga_plane(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + int vgacntrl = I915_READ(VGACNTRL); + uint8_t sr01; + + if (vgacntrl & VGA_DISP_DISABLE) + return; + /* + * Set SR01_SCREEN_OFF of SR1 register; + * Wait 30us; + */ + + I915_WRITE8(SRX_INDEX, SR01); + sr01 = I915_READ8(SRX_DATA); + I915_WRITE8(SRX_DATA, sr01 | SR01_SCREEN_OFF); + udelay(30); + /* disable center mode on 965GM and G4X platform */ + if (IS_I965GM(dev) || IS_G4X(dev)) + vgacntrl &= ~VGA_CENTER_ENABLE; + vgacntrl |= VGA_DISP_DISABLE; + + I915_WRITE(VGACNTRL, vgacntrl); + intel_wait_for_vblank(dev); +} + + static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) { struct drm_device *dev = crtc->dev; @@ -1342,7 +1370,7 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) //intel_crtc_dpms_video(crtc, FALSE); TODO /* Disable the VGA plane that we never use */ - I915_WRITE(VGACNTRL, VGA_DISP_DISABLE); + intel_crtc_disable_vga_plane(dev); /* Disable display plane */ temp = I915_READ(dspcntr_reg);