diff mbox

DRM/I915: Don't set the DPLL_MD multipler for LVDS output

Message ID 1251699198-29873-1-git-send-email-yakui.zhao@intel.com (mailing list archive)
State Accepted
Headers show

Commit Message

Zhao, Yakui Aug. 31, 2009, 6:13 a.m. UTC 
From: Zhao Yakui <yakui.zhao@intel.com>

When the output device is LVDS, maybe the pixel clock of adjusted_mode will be 
less than that in mode. In such case it will set the incorrect multipler factor
in DPLL_MD register.
So it is unnecessary to set dpll_md_reg when the output type is LVDS.

https://bugs.freedesktop.org/show_bug.cgi?id=22761

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Eric Anholt Sept. 4, 2009, 7:52 p.m. UTC | #1 
On Mon, 2009-08-31 at 14:13 +0800, yakui.zhao@intel.com wrote:
> From: Zhao Yakui <yakui.zhao@intel.com>
> 
> When the output device is LVDS, maybe the pixel clock of adjusted_mode will be 
> less than that in mode. In such case it will set the incorrect multipler factor
> in DPLL_MD register.
> So it is unnecessary to set dpll_md_reg when the output type is LVDS.

This seems wrong.  Now you leave whatever junk is currently in the
register there?

Seems like the right answer is:
if (IS_THING_WITH_DPLL_MD && is_sdvo) {
	I915_WRITE(dpll_md_reg, sdvo_pixel_multiply)
} else {
	I915_WRITE(dpll_md_reg, 0); // whatever means "multiply by one"
}

Also makes the change clear, because looking at it I figured you were
trying to solve an SDVO LVDS problem.
Zhao, Yakui Sept. 7, 2009, 12:42 a.m. UTC | #2 
On Sat, 2009-09-05 at 03:52 +0800, Eric Anholt wrote:
> On Mon, 2009-08-31 at 14:13 +0800, yakui.zhao@intel.com wrote:
> > From: Zhao Yakui <yakui.zhao@intel.com>
> > 
> > When the output device is LVDS, maybe the pixel clock of adjusted_mode will be 
> > less than that in mode. In such case it will set the incorrect multipler factor
> > in DPLL_MD register.
> > So it is unnecessary to set dpll_md_reg when the output type is LVDS.
> 
> This seems wrong.  Now you leave whatever junk is currently in the
> register there?
> 
> Seems like the right answer is:
> if (IS_THING_WITH_DPLL_MD && is_sdvo) {
> 	I915_WRITE(dpll_md_reg, sdvo_pixel_multiply)
> } else {
> 	I915_WRITE(dpll_md_reg, 0); // whatever means "multiply by one"
> }
> 
It is also right after this is limited to SDVO device.
When the output type is SDVO, we should set the correct DPLL multiplier.
In fact this is also applicable to  CRT/HDMI type. But as the pixel
clock of adjusted_mode is identical to that in mode for the CRT/HDMI, it
is unnecessary to set or it is set to zero.

Of course it is also ok if we limit it to the SDVO output device.

Thanks. 

> Also makes the change clear, because looking at it I figured you were
> trying to solve an SDVO LVDS problem.
>
diff mbox

Patch

Index: linux-2.6/drivers/gpu/drm/i915/intel_display.c
===================================================================
--- linux-2.6.orig/drivers/gpu/drm/i915/intel_display.c	2009-08-31 10:36:49.000000000 +0800
+++ linux-2.6/drivers/gpu/drm/i915/intel_display.c	2009-08-31 14:02:00.000000000 +0800
@@ -2633,7 +2633,7 @@ 
 		/* Wait for the clocks to stabilize. */
 		udelay(150);
 
-		if (IS_I965G(dev) && !IS_IGDNG(dev)) {
+		if (IS_I965G(dev) && !IS_IGDNG(dev) && !is_lvds) {
 			sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
 			I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
 					((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));