| Message ID | 1251774444-3215-1-git-send-email-zhenyuw@linux.intel.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
On Tue, 1 Sep 2009 11:07:24 +0800 Zhenyu Wang <zhenyuw@linux.intel.com> wrote: > It seems that on IGDNG the same swizzling setup always applys. > And front buffer tiling needs to set address swizzle in display > arb control too. > > Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_gem_tiling.c | 15 +++++++-------- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++ > 3 files changed, 24 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c > b/drivers/gpu/drm/i915/i915_gem_tiling.c index a2d527b..e774a4a 100644 > --- a/drivers/gpu/drm/i915/i915_gem_tiling.c > +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c > @@ -234,7 +234,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_device > *dev) uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; > bool need_disable; > > - if (!IS_I9XX(dev)) { > + if (IS_IGDNG(dev)) { > + /* On IGDNG whatever DRAM config, GPU always do > + * same swizzling setup. > + */ > + swizzle_x = I915_BIT_6_SWIZZLE_9_10; > + swizzle_y = I915_BIT_6_SWIZZLE_9; > + } else if (!IS_I9XX(dev)) { This doesn't seem equivalent... shouldn't it be if (IS_IGDNG(dev) || !IS_9XX)? > + if (IS_IGDNG(dev)) { > + /* must be set */ > + dspcntr |= DISPPLANE_TRICKLE_FEED_ENABLE; > + > + if (obj_priv->tiling_mode != I915_TILING_NONE) { > + int dsp_arb; > + dsp_arb = I915_READ(DISP_ARB_CTL); > + I915_WRITE(DISP_ARB_CTL, dsp_arb | > + DISP_TILE_SURFACE_SWIZZLING); > + } Do you need an else { int dsp_arb; dsp_arb = I915_READ(DISP_ARB_CTL); I915_WRITE(DISP_ARB_CTL, dsp_arb & (~DISP_TILE_SURFACE_SWIZZLING)); } for the non-tiled case? Or can you just set this once at setup time and forget it?
On Tue, 2009-09-01 at 08:41 -0700, Jesse Barnes wrote: > > - if (!IS_I9XX(dev)) { > > + if (IS_IGDNG(dev)) { > > + /* On IGDNG whatever DRAM config, GPU always do > > + * same swizzling setup. > > + */ > > + swizzle_x = I915_BIT_6_SWIZZLE_9_10; > > + swizzle_y = I915_BIT_6_SWIZZLE_9; > > + } else if (!IS_I9XX(dev)) { > > This doesn't seem equivalent... shouldn't it be if (IS_IGDNG(dev) > || !IS_9XX)? This puts the IGDNG code above the old 9XX code -- see the else if at the end of this sequence.
On Tue, 01 Sep 2009 09:19:04 -0700 Keith Packard <keithp@keithp.com> wrote: > On Tue, 2009-09-01 at 08:41 -0700, Jesse Barnes wrote: > > > > - if (!IS_I9XX(dev)) { > > > + if (IS_IGDNG(dev)) { > > > + /* On IGDNG whatever DRAM config, GPU always do > > > + * same swizzling setup. > > > + */ > > > + swizzle_x = I915_BIT_6_SWIZZLE_9_10; > > > + swizzle_y = I915_BIT_6_SWIZZLE_9; > > > + } else if (!IS_I9XX(dev)) { > > > > This doesn't seem equivalent... shouldn't it be if (IS_IGDNG(dev) > > || !IS_9XX)? > > This puts the IGDNG code above the old 9XX code -- see the else if at > the end of this sequence. Oh oops. Fail at reading diffs today...
On 2009.09.01 08:41:58 -0700, Jesse Barnes wrote: > Do you need an > > else { > int dsp_arb; > dsp_arb = I915_READ(DISP_ARB_CTL); > I915_WRITE(DISP_ARB_CTL, dsp_arb & > (~DISP_TILE_SURFACE_SWIZZLING)); > } > > for the non-tiled case? Or can you just set this once at setup time > and forget it? > Some draft testing showed we might just be sure it's setup whenever scan buffer tiling is enabled, so this bit is not one time setting, but to enable address swizzle if surface is tiling as is set in plane control. I'll send update patch. Thanks for reviewing this!
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index a2d527b..e774a4a 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -234,7 +234,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; bool need_disable; - if (!IS_I9XX(dev)) { + if (IS_IGDNG(dev)) { + /* On IGDNG whatever DRAM config, GPU always do + * same swizzling setup. + */ + swizzle_x = I915_BIT_6_SWIZZLE_9_10; + swizzle_y = I915_BIT_6_SWIZZLE_9; + } else if (!IS_I9XX(dev)) { /* As far as we know, the 865 doesn't have these bit 6 * swizzling issues. */ @@ -317,13 +323,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) } } - /* FIXME: check with memory config on IGDNG */ - if (IS_IGDNG(dev)) { - DRM_ERROR("disable tiling on IGDNG...\n"); - swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; - swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; - } - dev_priv->mm.bit_6_swizzle_x = swizzle_x; dev_priv->mm.bit_6_swizzle_y = swizzle_y; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 884757c..5303677 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1864,6 +1864,7 @@ #define DISPPLANE_NO_LINE_DOUBLE 0 #define DISPPLANE_STEREO_POLARITY_FIRST 0 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) +#define DISPPLANE_TRICKLE_FEED_ENABLE (1<<14) #define DISPPLANE_TILED (1<<10) #define DSPAADDR 0x70184 #define DSPASTRIDE 0x70188 @@ -2044,6 +2045,9 @@ #define GTIIR 0x44018 #define GTIER 0x4401c +#define DISP_ARB_CTL 0x45000 +#define DISP_TILE_SURFACE_SWIZZLING (1<<13) + /* PCH */ /* south display engine interrupt */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c4b17a7..124dfac 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1064,6 +1064,19 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, dspcntr &= ~DISPPLANE_TILED; } + if (IS_IGDNG(dev)) { + /* must be set */ + dspcntr |= DISPPLANE_TRICKLE_FEED_ENABLE; + + if (obj_priv->tiling_mode != I915_TILING_NONE) { + int dsp_arb; + dsp_arb = I915_READ(DISP_ARB_CTL); + I915_WRITE(DISP_ARB_CTL, dsp_arb | + DISP_TILE_SURFACE_SWIZZLING); + } + + } + I915_WRITE(dspcntr_reg, dspcntr); Start = obj_priv->gtt_offset;
It seems that on IGDNG the same swizzling setup always applys. And front buffer tiling needs to set address swizzle in display arb control too. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> --- drivers/gpu/drm/i915/i915_gem_tiling.c | 15 +++++++-------- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++ 3 files changed, 24 insertions(+), 8 deletions(-)