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[4/4] drm/I915: Write zero to DPLL_MD Reg for non-SDVO output

Message ID 1252568749-26949-4-git-send-email-yakui.zhao@intel.com (mailing list archive)
State Accepted
Headers show

Commit Message

Zhao, Yakui Sept. 10, 2009, 7:45 a.m. UTC 
From: Zhao Yakui <yakui.zhao@intel.com>

When the output device is LVDS, maybe the pixel clock of adjusted_mode will be 
less than that in mode. In such case it will set the incorrect multipler factor
in DPLL_MD register.
So the dpll_md_reg will be reset when the output type is non-SDVO

https://bugs.freedesktop.org/show_bug.cgi?id=22761

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewd-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/intel_display.c |    7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)
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Patch

Index: linux-2.6/drivers/gpu/drm/i915/intel_display.c
===================================================================
--- linux-2.6.orig/drivers/gpu/drm/i915/intel_display.c	2009-09-10 15:30:29.000000000 +0800
+++ linux-2.6/drivers/gpu/drm/i915/intel_display.c	2009-09-10 15:33:37.000000000 +0800
@@ -2652,9 +2652,12 @@ 
 		udelay(150);
 
 		if (IS_I965G(dev) && !IS_IGDNG(dev)) {
-			sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
-			I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
+			if (is_sdvo) {
+				sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
+				I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
 					((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
+			} else
+				I915_WRITE(dpll_md_reg, 0);
 		} else {
 			/* write it again -- the BIOS does, after all */
 			I915_WRITE(dpll_reg, dpll);