From patchwork Fri Nov 6 02:13:00 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhenyu Wang X-Patchwork-Id: 57986 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id nA62EKbn014360 for ; Fri, 6 Nov 2009 02:14:20 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BF0D1A0243; Thu, 5 Nov 2009 18:14:17 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fmsmga101.fm.intel.com (mga05.intel.com [192.55.52.89]) by gabe.freedesktop.org (Postfix) with ESMTP id D565EA0220 for ; Thu, 5 Nov 2009 18:14:12 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 05 Nov 2009 18:09:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.44,689,1249282800"; d="scan'208";a="511204340" Received: from unknown (HELO localhost.localdomain) ([10.239.36.125]) by fmsmga002.fm.intel.com with ESMTP; 05 Nov 2009 18:08:15 -0800 From: Zhenyu Wang To: eric@anholt.net Date: Fri, 6 Nov 2009 10:13:00 +0800 Message-Id: <1257473583-2746-4-git-send-email-zhenyuw@linux.intel.com> X-Mailer: git-send-email 1.6.2.5 In-Reply-To: <1257473583-2746-3-git-send-email-zhenyuw@linux.intel.com> References: <1257473583-2746-1-git-send-email-zhenyuw@linux.intel.com> <1257473583-2746-2-git-send-email-zhenyuw@linux.intel.com> <1257473583-2746-3-git-send-email-zhenyuw@linux.intel.com> Cc: intel-gfx@lists.freedesktop.org, Stable Team Subject: [Intel-gfx] [PATCH 3/6] drm/i915: HDMI hardware workaround for Ironlake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.9 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 663ab6d..c33451a 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -77,14 +77,32 @@ static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv; u32 temp; - if (mode != DRM_MODE_DPMS_ON) { - temp = I915_READ(hdmi_priv->sdvox_reg); + temp = I915_READ(hdmi_priv->sdvox_reg); + + /* HW workaround, need to toggle enable bit off and on for 12bpc, but + * we do this anyway which shows more stable in testing. + */ + if (IS_IGDNG(dev)) { I915_WRITE(hdmi_priv->sdvox_reg, temp & ~SDVO_ENABLE); + POSTING_READ(hdmi_priv->sdvox_reg); + } + + if (mode != DRM_MODE_DPMS_ON) { + temp &= ~SDVO_ENABLE; } else { - temp = I915_READ(hdmi_priv->sdvox_reg); - I915_WRITE(hdmi_priv->sdvox_reg, temp | SDVO_ENABLE); + temp |= SDVO_ENABLE; } + + I915_WRITE(hdmi_priv->sdvox_reg, temp); POSTING_READ(hdmi_priv->sdvox_reg); + + /* HW workaround, need to write this twice for issue that may result + * in first write getting masked. + */ + if (IS_IGDNG(dev)) { + I915_WRITE(hdmi_priv->sdvox_reg, temp); + POSTING_READ(hdmi_priv->sdvox_reg); + } } static void intel_hdmi_save(struct drm_connector *connector)