@@ -2488,8 +2488,7 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
int total_size, cacheline_size;
int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
struct intel_watermark_params planea_params, planeb_params;
- unsigned long line_time_us;
- int sr_clock, sr_entries = 0, entries_required;
+ int sr_clock, srwm = 8, entries_required;
/* Create copies of the base settings for each pipe */
planea_params = planeb_params = g4x_wm_info;
@@ -2517,7 +2516,7 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
cursora_wm = cursorb_wm = 16;
cursor_sr = 32;
- DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
+ DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
/* Calc sr entries for one plane configs */
if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
@@ -2525,23 +2524,21 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
const static int sr_latency_ns = 12000;
sr_clock = planea_clock ? planea_clock : planeb_clock;
- line_time_us = ((sr_hdisplay * 1000) / sr_clock);
- /* Use ns/us then divide to preserve precision */
- sr_entries = (((sr_latency_ns / line_time_us) + 1) *
- pixel_size * sr_hdisplay) / 1000;
- sr_entries = roundup(sr_entries / cacheline_size, 1);
- DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
+ srwm = intel_calculate_wm(sr_clock, &g4x_wm_info,
+ pixel_size, sr_latency_ns);
+
+ DRM_DEBUG_KMS("self-refresh watermark: %d\n", srwm);
I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
}
- DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
- planea_wm, planeb_wm, sr_entries);
+ DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
+ planea_wm, planeb_wm, srwm);
planea_wm &= 0x3f;
planeb_wm &= 0x3f;
- I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
+ I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
(cursorb_wm << DSPFW_CURSORB_SHIFT) |
(planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
@@ -2555,26 +2552,20 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
int planeb_clock, int sr_hdisplay, int pixel_size)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- unsigned long line_time_us;
- int sr_clock, sr_entries, srwm = 1;
+ int sr_clock, srwm = 8, cursor_srwm;
+ cursor_srwm = 16;
/* Calc sr entries for one plane configs */
if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
/* self-refresh has much higher latency */
const static int sr_latency_ns = 12000;
sr_clock = planea_clock ? planea_clock : planeb_clock;
- line_time_us = ((sr_hdisplay * 1000) / sr_clock);
-
- /* Use ns/us then divide to preserve precision */
- sr_entries = (((sr_latency_ns / line_time_us) + 1) *
- pixel_size * sr_hdisplay) / 1000;
- sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
- DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
- srwm = I945_FIFO_SIZE - sr_entries;
- if (srwm < 0)
- srwm = 1;
- srwm &= 0x3f;
+
+ srwm = intel_calculate_wm(sr_clock, &i945_wm_info,
+ pixel_size, sr_latency_ns);
+ DRM_DEBUG_KMS("self-refresh watermark: %d\n", srwm);
+
I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
}
@@ -2585,6 +2576,8 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
(8 << 0));
I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
+ /* Write the cursor self-refresh watermark */
+ I915_WRITE(DSPFW3, (cursor_srwm << 24));
}
static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
@@ -2596,8 +2589,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
int total_size, cacheline_size, cwm, srwm = 1;
int planea_wm, planeb_wm;
struct intel_watermark_params planea_params, planeb_params;
- unsigned long line_time_us;
- int sr_clock, sr_entries = 0;
+ int sr_clock;
/* Create copies of the base settings for each pipe */
if (IS_I965GM(dev) || IS_I945GM(dev))
@@ -2633,16 +2625,10 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
const static int sr_latency_ns = 6000;
sr_clock = planea_clock ? planea_clock : planeb_clock;
- line_time_us = ((sr_hdisplay * 1000) / sr_clock);
-
- /* Use ns/us then divide to preserve precision */
- sr_entries = (((sr_latency_ns / line_time_us) + 1) *
- pixel_size * sr_hdisplay) / 1000;
- sr_entries = roundup(sr_entries / cacheline_size, 1);
- DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
- srwm = total_size - sr_entries;
- if (srwm < 0)
- srwm = 1;
+
+ srwm = intel_calculate_wm(sr_clock, &planea_params,
+ pixel_size, sr_latency_ns);
+ DRM_DEBUG_KMS("self-refresh watermark: %d\n", srwm);
I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
}