From patchwork Wed Dec 2 01:38:43 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Peng X-Patchwork-Id: 64086 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id nB22EhEE003591 for ; Wed, 2 Dec 2009 02:14:43 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 73EA89F385; Tue, 1 Dec 2009 18:14:43 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fmsmga102.fm.intel.com (mga10.intel.com [192.55.52.92]) by gabe.freedesktop.org (Postfix) with ESMTP id 6AADB9F020 for ; Tue, 1 Dec 2009 18:14:41 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 01 Dec 2009 18:10:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.47,324,1257148800"; d="scan'208";a="751945019" Received: from ubuntu-pli1.bj.intel.com (HELO [172.16.180.114]) ([172.16.180.114]) by fmsmga001.fm.intel.com with ESMTP; 01 Dec 2009 18:14:39 -0800 From: Li Peng To: intel-gfx Date: Wed, 02 Dec 2009 09:38:43 +0800 Message-Id: <1259717923.6468.4.camel@ubuntu-pli1.bj.intel.com> Mime-Version: 1.0 X-Mailer: Evolution 2.10.1 Subject: [Intel-gfx] [PATCH] drm/i915: enable memory self refresh on 945GM X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.9 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1687edf..93b5077 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -301,7 +301,9 @@ #define FW_BLC 0x020d8 #define FW_BLC2 0x020dc #define FW_BLC_SELF 0x020e0 /* 915+ only */ -#define FW_BLC_SELF_EN (1<<15) +#define FW_BLC_SELF_EN_MASK (1<<31) +#define FW_BLC_SELF_FIFO_MASK (1<<16) +#define FW_BLC_SELF_EN (1<<15) #define MM_BURST_LENGTH 0x00700000 #define MM_FIFO_WATERMARK 0x0001F000 #define LM_BURST_LENGTH 0x00000700 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3ba6546..9b96439 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2580,7 +2580,10 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, srwm = total_size - sr_entries; if (srwm < 0) srwm = 1; - I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); + if (IS_I945GM(dev)) + I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); + else + I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); } DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", @@ -3671,11 +3674,23 @@ static void intel_gpu_idle_timer(unsigned long arg) void intel_increase_renderclock(struct drm_device *dev, bool schedule) { drm_i915_private_t *dev_priv = dev->dev_private; + u32 fw_blc_self; + int need_schedule = 0; if (IS_IGDNG(dev)) return; + if (IS_I945GM(dev)) { + DRM_DEBUG("disable memory self refresh on 945\n"); + fw_blc_self = I915_READ(FW_BLC_SELF); + fw_blc_self &= ~FW_BLC_SELF_EN; + I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); + need_schedule = 1; + } + if (!dev_priv->render_reclock_avail) { + if (need_schedule) + goto schedule_timer; DRM_DEBUG("not reclocking render clock\n"); return; } @@ -3688,6 +3703,7 @@ void intel_increase_renderclock(struct drm_device *dev, bool schedule) DRM_DEBUG("increasing render clock frequency\n"); /* Schedule downclock */ +schedule_timer: if (schedule) mod_timer(&dev_priv->idle_timer, jiffies + msecs_to_jiffies(GPU_IDLE_TIMEOUT)); @@ -3700,6 +3716,11 @@ void intel_decrease_renderclock(struct drm_device *dev) if (IS_IGDNG(dev)) return; + if (IS_I945GM(dev)) { + DRM_DEBUG("enable memory self refresh on 945\n"); + I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); + } + if (!dev_priv->render_reclock_avail) { DRM_DEBUG("not reclocking render clock\n"); return;