[v2,4/9] drm/i915: Use the required entry size correctly on the different platforms

Commit Message

Zhao, Yakui Jan. 20, 2010, 9:41 a.m. UTC

None

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 43ec351..167b35a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2132,12 +2132,18 @@  ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
 }
 
 
+enum wm_fifo_type {
+	WM_USE_OFFSET = 0,
+	WM_USE_ENTRY_COUNT,
+};
+
 struct intel_watermark_params {
 	unsigned long fifo_size;
 	unsigned long max_wm;
 	unsigned long default_wm;
 	unsigned long guard_size;
 	unsigned long cacheline_size;
+	enum wm_fifo_type fifo_type;
 };
 
 /* Pineview has different values for various configs */
@@ -2146,14 +2152,16 @@  static struct intel_watermark_params pineview_display_wm = {
 	PINEVIEW_MAX_WM,
 	PINEVIEW_DFT_WM,
 	PINEVIEW_GUARD_WM,
-	PINEVIEW_FIFO_LINE_SIZE
+	PINEVIEW_FIFO_LINE_SIZE,
+	WM_USE_OFFSET,
 };
 static struct intel_watermark_params pineview_display_hplloff_wm = {
 	PINEVIEW_DISPLAY_FIFO,
 	PINEVIEW_MAX_WM,
 	PINEVIEW_DFT_HPLLOFF_WM,
 	PINEVIEW_GUARD_WM,
-	PINEVIEW_FIFO_LINE_SIZE
+	PINEVIEW_FIFO_LINE_SIZE,
+	WM_USE_OFFSET,
 };
 static struct intel_watermark_params pineview_cursor_wm = {
 	PINEVIEW_CURSOR_FIFO,
@@ -2161,48 +2169,57 @@  static struct intel_watermark_params pineview_cursor_wm = {
 	PINEVIEW_CURSOR_DFT_WM,
 	PINEVIEW_CURSOR_GUARD_WM,
 	PINEVIEW_FIFO_LINE_SIZE,
+	WM_USE_OFFSET,
 };
 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
 	PINEVIEW_CURSOR_FIFO,
 	PINEVIEW_CURSOR_MAX_WM,
 	PINEVIEW_CURSOR_DFT_WM,
 	PINEVIEW_CURSOR_GUARD_WM,
-	PINEVIEW_FIFO_LINE_SIZE
+	PINEVIEW_FIFO_LINE_SIZE,
+	WM_USE_OFFSET,
 };
+
 static struct intel_watermark_params g4x_wm_info = {
 	G4X_FIFO_SIZE,
 	G4X_MAX_WM,
 	G4X_MAX_WM,
 	2,
 	G4X_FIFO_LINE_SIZE,
+	WM_USE_ENTRY_COUNT,
 };
+
 static struct intel_watermark_params i945_wm_info = {
 	I945_FIFO_SIZE,
 	I915_MAX_WM,
 	1,
 	2,
-	I915_FIFO_LINE_SIZE
+	I915_FIFO_LINE_SIZE,
+	WM_USE_OFFSET,
 };
 static struct intel_watermark_params i915_wm_info = {
 	I915_FIFO_SIZE,
 	I915_MAX_WM,
 	1,
 	2,
-	I915_FIFO_LINE_SIZE
+	I915_FIFO_LINE_SIZE,
+	WM_USE_OFFSET,
 };
 static struct intel_watermark_params i855_wm_info = {
 	I855GM_FIFO_SIZE,
 	I915_MAX_WM,
 	1,
 	2,
-	I830_FIFO_LINE_SIZE
+	I830_FIFO_LINE_SIZE,
+	WM_USE_OFFSET,
 };
 static struct intel_watermark_params i830_wm_info = {
 	I830_FIFO_SIZE,
 	I915_MAX_WM,
 	1,
 	2,
-	I830_FIFO_LINE_SIZE
+	I830_FIFO_LINE_SIZE,
+	WM_USE_OFFSET,
 };
 
 /**
@@ -2229,6 +2246,7 @@  static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 					unsigned long latency_ns)
 {
 	long entries_required, wm_size;
+	int sr_entries;
 
 	/*
 	 * Note: we need to make sure we don't overflow for various clock &
@@ -2238,11 +2256,15 @@  static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 	 */
 	entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 		1000;
-	entries_required /= wm->cacheline_size;
+	/* Round up to the next cacheline boundary */
+	sr_entries = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 
 	DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
 
-	wm_size = wm->fifo_size - (entries_required + wm->guard_size);
+	if (wm->fifo_type == WM_USE_ENTRY_COUNT)
+		wm_size = sr_entries + wm->guard_size;
+	else
+		wm_size = wm->fifo_size - (sr_entries + wm->guard_size);
 
 	DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);