From patchwork Thu Feb 4 21:05:11 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 77211 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o14L67PQ009070 for ; Thu, 4 Feb 2010 21:06:47 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 32F4D9F5C3; Thu, 4 Feb 2010 13:05:52 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail.ffwll.ch (cable-static-49-187.intergga.ch [157.161.49.187]) by gabe.freedesktop.org (Postfix) with ESMTP id DE56F9F5C0 for ; Thu, 4 Feb 2010 13:05:47 -0800 (PST) Received: by mail.ffwll.ch (Postfix, from userid 1000) id E440A20C2BD; Thu, 4 Feb 2010 22:05:46 +0100 (CET) X-Spam-ASN: X-Spam-Checker-Version: SpamAssassin 3.2.5 (2008-06-10) on orange.ffwll.ch X-Spam-Level: X-Spam-Hammy: 0.000-+--struct, 0.000-+--100644, 0.000-+--signed-off-by X-Spam-Status: No, score=-1.2 required=6.0 tests=ALL_TRUSTED,BAYES_00, FH_DATE_PAST_20XX autolearn=no version=3.2.5 X-Spam-Spammy: 0.970-+--H*m:ffwll, 0.965-+--H*Ad:U*daniel.vetter, 0.955-+--H*r:mail.ffwll.ch Received: from biene (unknown [192.168.23.129]) by mail.ffwll.ch (Postfix) with ESMTP id 52EFC20C2C0; Thu, 4 Feb 2010 22:05:19 +0100 (CET) Received: from daniel by biene with local (Exim 4.71) (envelope-from ) id 1Nd8t8-0004hn-L9; Thu, 04 Feb 2010 22:05:22 +0100 From: Daniel Vetter To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Feb 2010 22:05:11 +0100 Message-Id: <1265317513-27723-12-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.6.6.1 In-Reply-To: <1265317513-27723-11-git-send-email-daniel.vetter@ffwll.ch> References: <1265317513-27723-1-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-2-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-3-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-4-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-5-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-6-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-7-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-8-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-9-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-10-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-11-git-send-email-daniel.vetter@ffwll.ch> Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 11/13] drm/i915: pipelined fencing, part 1: fence stealing X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.9 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 04 Feb 2010 21:06:47 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f26a037..c684d0e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -871,8 +871,8 @@ void i915_gem_release_mmap(struct drm_gem_object *obj); void i915_gem_lastclose(struct drm_device *dev); uint32_t i915_get_gem_seqno(struct drm_device *dev); bool i915_seqno_passed(uint32_t seq1, uint32_t seq2); -int i915_gem_object_get_fence_reg(struct drm_gem_object *obj); -int i915_gem_object_put_fence_reg(struct drm_gem_object *obj); +int i915_gem_object_get_fence_reg(struct drm_gem_object *obj, int pipelined); +int i915_gem_object_put_fence_reg(struct drm_gem_object *obj, int pipelined); void i915_gem_retire_requests(struct drm_device *dev); void i915_gem_retire_work_handler(struct work_struct *work); void i915_gem_clflush_object(struct drm_gem_object *obj); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 83c7d58..1fd7a65 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -49,7 +49,8 @@ static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *o static int i915_gem_object_wait_rendering(struct drm_gem_object *obj); static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment); -static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); +static void i915_gem_clear_fence_reg(struct drm_gem_object *obj, + int pipelined); static int i915_gem_evict_something(struct drm_device *dev, int min_size); static int i915_gem_evict_from_inactive_list(struct drm_device *dev); static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, @@ -1215,7 +1216,7 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) /* Need a new fence register? */ if (obj_priv->tiling_mode != I915_TILING_NONE) { - ret = i915_gem_object_get_fence_reg(obj); + ret = i915_gem_object_get_fence_reg(obj, 0); if (ret) goto unlock; } @@ -2075,7 +2076,7 @@ i915_gem_object_unbind(struct drm_gem_object *obj) /* release the fence reg _after_ flushing */ if (obj_priv->fence_reg != I915_FENCE_REG_NONE) - i915_gem_clear_fence_reg(obj); + i915_gem_clear_fence_reg(obj, 0); if (obj_priv->agp_mem != NULL) { drm_unbind_agp(obj_priv->agp_mem); @@ -2426,7 +2427,7 @@ static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); } -static int i915_find_fence_reg(struct drm_device *dev) +static int i915_find_fence_reg(struct drm_device *dev, int pipelined) { struct drm_i915_fence_reg *reg = NULL; struct drm_i915_gem_object *obj_priv = NULL; @@ -2471,7 +2472,7 @@ static int i915_find_fence_reg(struct drm_device *dev) * under us. */ drm_gem_object_reference(obj); - ret = i915_gem_object_put_fence_reg(obj); + ret = i915_gem_object_put_fence_reg(obj, pipelined); drm_gem_object_unreference(obj); if (ret != 0) return ret; @@ -2493,7 +2494,7 @@ static int i915_find_fence_reg(struct drm_device *dev) * and tiling format. */ int -i915_gem_object_get_fence_reg(struct drm_gem_object *obj) +i915_gem_object_get_fence_reg(struct drm_gem_object *obj, int pipelined) { struct drm_device *dev = obj->dev; struct drm_i915_private *dev_priv = dev->dev_private; @@ -2528,7 +2529,7 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj) break; } - ret = i915_find_fence_reg(dev); + ret = i915_find_fence_reg(dev, pipelined); if (ret < 0) return ret; @@ -2538,6 +2539,12 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj) reg->obj = obj; + if (pipelined && reg->last_rendering_seqno != 0) { + ret = i915_wait_request(dev, reg->last_rendering_seqno); + if (ret != 0) + return ret; + } + if (IS_I965G(dev)) i965_write_fence_reg(reg); else if (IS_I9XX(dev)) @@ -2559,7 +2566,7 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj) * data structures in dev_priv and obj_priv. */ static void -i915_gem_clear_fence_reg(struct drm_gem_object *obj) +i915_gem_clear_fence_reg(struct drm_gem_object *obj, int pipelined) { struct drm_device *dev = obj->dev; drm_i915_private_t *dev_priv = dev->dev_private; @@ -2567,6 +2574,8 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj) struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[obj_priv->fence_reg]; + if (pipelined) + goto end; if (IS_I965G(dev)) I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); else { @@ -2581,6 +2590,7 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj) I915_WRITE(fence_reg, 0); } +end: reg->obj = NULL; obj_priv->fence_reg = I915_FENCE_REG_NONE; list_del_init(®->lru_list); @@ -2595,7 +2605,8 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj) * data structures in dev_priv and obj_priv. */ int -i915_gem_object_put_fence_reg(struct drm_gem_object *obj) +i915_gem_object_put_fence_reg(struct drm_gem_object *obj, + int pipelined) { struct drm_i915_gem_object *obj_priv = obj->driver_private; @@ -2611,13 +2622,13 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj) if (obj_priv->fenced_gpu_access) { int ret; - ret = i915_gem_object_flush_gpu_write_domain(obj, 0); + ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined); if (ret != 0) return ret; } i915_gem_object_flush_gtt_write_domain(obj); - i915_gem_clear_fence_reg (obj); + i915_gem_clear_fence_reg(obj, pipelined); return 0; } @@ -3317,7 +3328,7 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, * properly handle blits to/from tiled surfaces. */ if (need_fence) { - ret = i915_gem_object_get_fence_reg(obj); + ret = i915_gem_object_get_fence_reg(obj, 1); if (ret != 0) { if (ret != -EBUSY && ret != -ERESTARTSYS) DRM_ERROR("Failure to install fence: %d\n", diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index b0cbe3a..6879f04 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -362,7 +362,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, if (!i915_gem_object_fence_offset_ok(obj, args->tiling_mode)) ret = i915_gem_object_unbind(obj); else - ret = i915_gem_object_put_fence_reg(obj); + ret = i915_gem_object_put_fence_reg(obj, 0); if (ret != 0) { WARN(ret != -ERESTARTSYS, "failed to reset object for tiling switch"); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9dc2eed..fd870d0 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1149,7 +1149,9 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj) */ if (obj_priv->fence_reg == I915_FENCE_REG_NONE && obj_priv->tiling_mode != I915_TILING_NONE) { - ret = i915_gem_object_get_fence_reg(obj); + /* FIXME: Check whether pipelined fencing makes + * sense for the pageflip. */ + ret = i915_gem_object_get_fence_reg(obj, 0); if (ret != 0) { i915_gem_object_unpin(obj); return ret;