From patchwork Thu Feb 4 21:05:13 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 77215 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o14L6C2Z009437 for ; Thu, 4 Feb 2010 21:06:52 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6EBBE9F5CC; Thu, 4 Feb 2010 13:06:09 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail.ffwll.ch (cable-static-49-187.intergga.ch [157.161.49.187]) by gabe.freedesktop.org (Postfix) with ESMTP id 7FBEF9F599 for ; Thu, 4 Feb 2010 13:06:07 -0800 (PST) Received: by mail.ffwll.ch (Postfix, from userid 1000) id 675E420C2C3; Thu, 4 Feb 2010 22:06:06 +0100 (CET) X-Spam-ASN: X-Spam-Checker-Version: SpamAssassin 3.2.5 (2008-06-10) on orange.ffwll.ch X-Spam-Level: X-Spam-Hammy: 0.000-+--struct, 0.000-+--100644, 0.000-+--signed-off-by X-Spam-Status: No, score=-1.2 required=6.0 tests=ALL_TRUSTED,BAYES_00, FH_DATE_PAST_20XX autolearn=no version=3.2.5 X-Spam-Spammy: 0.970-+--H*m:ffwll, 0.965-+--H*Ad:U*daniel.vetter, 0.955-+--H*r:mail.ffwll.ch Received: from biene (unknown [192.168.23.129]) by mail.ffwll.ch (Postfix) with ESMTP id 5C85C20C2C2; Thu, 4 Feb 2010 22:05:20 +0100 (CET) Received: from daniel by biene with local (Exim 4.71) (envelope-from ) id 1Nd8tA-0004jt-7x; Thu, 04 Feb 2010 22:05:24 +0100 From: Daniel Vetter To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Feb 2010 22:05:13 +0100 Message-Id: <1265317513-27723-14-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.6.6.1 In-Reply-To: <1265317513-27723-13-git-send-email-daniel.vetter@ffwll.ch> References: <1265317513-27723-1-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-2-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-3-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-4-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-5-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-6-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-7-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-8-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-9-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-10-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-11-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-12-git-send-email-daniel.vetter@ffwll.ch> <1265317513-27723-13-git-send-email-daniel.vetter@ffwll.ch> Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 13/13] drm/i915: pipelined fencing, part 2: fence setup X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.9 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 04 Feb 2010 21:06:52 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 5e90587..483b520 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2339,7 +2339,7 @@ i915_gem_object_get_pages(struct drm_gem_object *obj) return 0; } -static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) +static void i965_write_fence_reg(struct drm_i915_fence_reg *reg, int pipelined) { struct drm_gem_object *obj = reg->obj; struct drm_device *dev = obj->dev; @@ -2347,6 +2347,7 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) struct drm_i915_gem_object *obj_priv = obj->driver_private; int regnum = obj_priv->fence_reg; uint64_t val; + RING_LOCALS; val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & 0xfffff000) << 32; @@ -2356,10 +2357,20 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) val |= 1 << I965_FENCE_TILING_Y_SHIFT; val |= I965_FENCE_REG_VALID; - I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); + if (pipelined) { + BEGIN_LP_RING(6); + OUT_RING(MI_LOAD_REGISTER_IMM); + OUT_RING(FENCE_REG_965_0 + (regnum * 8)); + OUT_RING((uint32_t) val); + OUT_RING(MI_LOAD_REGISTER_IMM); + OUT_RING(FENCE_REG_965_0 + (regnum * 8) + 4); + OUT_RING((uint32_t) (val >> 32)); + ADVANCE_LP_RING(); + } else + I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); } -static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) +static void i915_write_fence_reg(struct drm_i915_fence_reg *reg, int pipelined) { struct drm_gem_object *obj = reg->obj; struct drm_device *dev = obj->dev; @@ -2369,6 +2380,7 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) int tile_width; uint32_t fence_reg, val; uint32_t pitch_val; + RING_LOCALS; if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || (obj_priv->gtt_offset & (obj->size - 1))) { @@ -2398,10 +2410,18 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) fence_reg = FENCE_REG_830_0 + (regnum * 4); else fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); - I915_WRITE(fence_reg, val); + + if (pipelined) { + BEGIN_LP_RING(3); + OUT_RING(MI_LOAD_REGISTER_IMM); + OUT_RING(fence_reg); + OUT_RING(val); + ADVANCE_LP_RING(); + } else + I915_WRITE(fence_reg, val); } -static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) +static void i830_write_fence_reg(struct drm_i915_fence_reg *reg, int pipelined) { struct drm_gem_object *obj = reg->obj; struct drm_device *dev = obj->dev; @@ -2411,6 +2431,7 @@ static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) uint32_t val; uint32_t pitch_val; uint32_t fence_size_bits; + RING_LOCALS; if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || (obj_priv->gtt_offset & (obj->size - 1))) { @@ -2432,7 +2453,14 @@ static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) val |= pitch_val << I830_FENCE_PITCH_SHIFT; val |= I830_FENCE_REG_VALID; - I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); + if (pipelined) { + BEGIN_LP_RING(3); + OUT_RING(MI_LOAD_REGISTER_IMM); + OUT_RING(FENCE_REG_830_0 + (regnum * 4)); + OUT_RING(val); + ADVANCE_LP_RING(); + } else + I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); } static int i915_find_fence_reg(struct drm_device *dev, int pipelined) @@ -2517,6 +2545,14 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj, int pipelined) /* Wait for the gpu to setup the fence it it was pipelined. */ if (!pipelined && reg->setup_seqno != 0) { + /* With certain error conditions, the request might not + * yet have been emitted. */ + if (reg->setup_seqno == dev_priv->mm.next_gem_seqno) { + uint32_t seqno = i915_add_request(dev, NULL); + if (seqno == 0) + return -ENOMEM; + } + ret = i915_wait_request(dev, reg->setup_seqno); if (ret != 0) return ret; @@ -2562,18 +2598,12 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj, int pipelined) else reg->setup_seqno = 0; - if (pipelined && reg->last_rendering_seqno != 0) { - ret = i915_wait_request(dev, reg->last_rendering_seqno); - if (ret != 0) - return ret; - } - if (IS_I965G(dev)) - i965_write_fence_reg(reg); + i965_write_fence_reg(reg, pipelined); else if (IS_I9XX(dev)) - i915_write_fence_reg(reg); + i915_write_fence_reg(reg, pipelined); else - i830_write_fence_reg(reg); + i830_write_fence_reg(reg, pipelined); trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, obj_priv->tiling_mode);