[2/3] drm/intel: Attempt to use 10-bit gamma palette mode

Commit Message

Peter Clifton April 26, 2010, 10:24 p.m. UTC

None

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ab1bd2d..7a0c6ac 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1766,6 +1766,9 @@ 
 #define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
 #define   PIPECONF_INTERLACE_FIELD_0_ONLY		(7 << 21)
 #define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)
+#define PIPEAGCMAXRED		0x70010
+#define PIPEAGCMAXGREEN		0x70014
+#define PIPEAGCMAXBLUE		0x70018
 #define PIPEASTAT		0x70024
 #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
 #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
@@ -1958,13 +1961,15 @@ 
 /* Pipe B */
 #define PIPEBDSL		0x71000
 #define PIPEBCONF		0x71008
+#define PIPEBGCMAXRED		0x71010
+#define PIPEBGCMAXGREEN		0x71014
+#define PIPEBGCMAXBLUE		0x71018
 #define PIPEBSTAT		0x71024
 #define PIPEBFRAMEHIGH		0x71040
 #define PIPEBFRAMEPIXEL		0x71044
 #define PIPEB_FRMCOUNT_GM45	0x71040
 #define PIPEB_FLIPCOUNT_GM45	0x71044
 
-
 /* Display B control */
 #define DSPBCNTR		0x71180
 #define   DISPPLANE_ALPHA_TRANS_ENABLE		(1<<15)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 456f738..5e8191a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3433,6 +3433,9 @@  void intel_crtc_load_lut(struct drm_crtc *crtc)
 	int pipe = intel_crtc->pipe;
 	int pal_reg = (pipe == 0) ? PALETTE_A : PALETTE_B;
 	int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
+	int maxr_reg = (pipe == 0) ? PIPEAGCMAXRED : PIPEBGCMAXRED;
+	int maxg_reg = (pipe == 0) ? PIPEAGCMAXGREEN : PIPEBGCMAXGREEN;
+	int maxb_reg = (pipe == 0) ? PIPEAGCMAXBLUE : PIPEBGCMAXBLUE;
 	int pipeconf = I915_READ(pipeconf_reg);
 	int i;
 
@@ -3445,17 +3448,33 @@  void intel_crtc_load_lut(struct drm_crtc *crtc)
 		pal_reg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
 						    LGC_PALETTE_B;
 
-	/* Switch to 8-bit gamma mode */
-	pipeconf &= ~PIPEACONF_GAMMA;
+	/* Switch to 10-bit gamma mode */
+	pipeconf |= PIPEACONF_GAMMA;
 	I915_WRITE(pipeconf_reg, pipeconf);
 	I915_READ(pipeconf_reg);
 
-	for (i = 0; i < 256; i++) {
-		I915_WRITE(pal_reg + 4 * i,
-			   ((intel_crtc->lut_r[i] >> 8) << 16) |
-			   ((intel_crtc->lut_g[i] >> 8) << 8) |
-			   (intel_crtc->lut_b[i] >> 8));
+	/* Use every other value from the LUT passed,
+	 * 10-bit mode uses 128 entries. */
+	for (i = 0; i < 128; i++) {
+		I915_WRITE(pal_reg + 8 * i,
+			   ((intel_crtc->lut_r[2 * i] & 0xFF) << 16) |
+			   ((intel_crtc->lut_g[2 * i] & 0xFF) << 8) |
+			   (intel_crtc->lut_b[2 * i] & 0xFF));
+		I915_WRITE(pal_reg + 8 * i + 4,
+			   ((intel_crtc->lut_r[2 * i] >> 8) << 16) |
+			   ((intel_crtc->lut_g[2 * i] >> 8) << 8) |
+			   (intel_crtc->lut_b[2 * i] >> 8));
 	}
+
+	/* FIXME: Distortion here, we're trying to get 129 evenly spaced
+	 * samples from a LUT with 256 entries. We use 0, 2, 4 ... 254,
+	 * for the main palette, then entry 255 for this last register.
+	 */
+	/* Note that these registers _could_ take the LUT value of
+	 * 1024, but we're maxing out at 1023.984375 as it is easier. */
+	I915_WRITE(maxr_reg, intel_crtc->lut_r[255]);
+	I915_WRITE(maxg_reg, intel_crtc->lut_g[255]);
+	I915_WRITE(maxb_reg, intel_crtc->lut_b[255]);
 }
 
 static int intel_crtc_cursor_set(struct drm_crtc *crtc,