[21/23] intel-gtt: use chipset generation number some more

Commit Message

Daniel Vetter Sept. 1, 2010, 8:30 p.m. UTC

None

Patch

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 6e93f95..2aca66c 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -559,8 +559,7 @@  static unsigned int intel_gtt_stolen_entries(void)
 			stolen_size = 0;
 			break;
 		}
-	} else if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||
-		   intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) {
+	} else if (INTEL_GTT_GEN == 6) {
 		/*
 		 * SandyBridge has new memory control reg at 0x50.w
 		 */
@@ -752,20 +751,14 @@  static unsigned int intel_gtt_mappable_entries(void)
 	pci_read_config_word(intel_private.bridge_dev,
 			     I830_GMCH_CTRL, &gmch_ctrl);
 
-	switch (intel_private.pcidev->device) {
-	case PCI_DEVICE_ID_INTEL_82830_CGC:
-	case PCI_DEVICE_ID_INTEL_82845G_IG:
-	case PCI_DEVICE_ID_INTEL_82855GM_IG:
-	case PCI_DEVICE_ID_INTEL_82865_IG:
+	if (INTEL_GTT_GEN == 2) {
 		if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
 			aperture_size *= 64;
 		else
 			aperture_size *= 128;
-		break;
-	default:
+	} else {
 		/* 9xx supports large sizes, just look at the length */
 		aperture_size = pci_resource_len(intel_private.pcidev, 2);
-		break;
 	}
 
 	return aperture_size >> PAGE_SHIFT;