From patchwork Sat Sep 4 13:19:17 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 155791 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id o84DID4X012807 for ; Sat, 4 Sep 2010 13:18:49 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 496949E93E for ; Sat, 4 Sep 2010 06:18:13 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (server109-228-6-236.live-servers.net [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id 8AED79E77F for ; Sat, 4 Sep 2010 06:17:57 -0700 (PDT) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.66.37; Received: from arrandale.alporthouse.com (unverified [78.156.66.37]) by fireflyinternet.com (Firefly Internet SMTP) with ESMTP id 6663031-1500050 for multiple; Sat, 04 Sep 2010 14:18:39 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Sat, 4 Sep 2010 14:19:17 +0100 Message-Id: <1283606357-2134-1-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 1.7.1 X-Originating-IP: 78.156.66.37 Subject: [Intel-gfx] [PATCH] agp/intel: Correctly initialise the IFP resource for allocation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Sat, 04 Sep 2010 13:18:49 +0000 (UTC) diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index d22ffb8..8f27ebc 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -68,7 +68,9 @@ static struct _intel_private { struct page *i8xx_page; struct resource ifp_resource; int resource_valid; -} intel_private; +} intel_private = { + .ifp_resource = { .name = "Isoch Flush Page", .flags = IORESOURCE_MEM } +}; #ifdef USE_PCI_DMA_API static int intel_agp_map_page(struct page *page, dma_addr_t *ret) @@ -986,65 +988,85 @@ static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type) static int intel_alloc_chipset_flush_resource(void) { int ret; - ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE, - PAGE_SIZE, PCIBIOS_MIN_MEM, 0, - pcibios_align_resource, agp_bridge->dev); + + ret = pci_bus_alloc_resource(agp_bridge->dev->bus, + &intel_private.ifp_resource, + PAGE_SIZE, PAGE_SIZE, + PCIBIOS_MIN_MEM, 0, + pcibios_align_resource, + agp_bridge->dev); + if (ret) { + dev_err(&intel_private.pcidev->dev, + "Failed to allocate Isoch Flush Page: %d.", + ret); + intel_private.resource_valid = 0; + } return ret; } -static void intel_i915_setup_chipset_flush(void) +static int intel_request_chipset_flush_resource(u64 addr) { int ret; + + intel_private.ifp_resource.start = addr; + intel_private.ifp_resource.end = addr + PAGE_SIZE; + + ret = request_resource(&iomem_resource, &intel_private.ifp_resource); + /* some BIOSes reserve this area in a pnp some don't */ + if (ret) { + dev_err(&intel_private.pcidev->dev, + "Failed to request Isoch Flush Page: %d.", + ret); + intel_private.resource_valid = 0; + } + + return ret; +} + +static void intel_i915_setup_chipset_flush(void) +{ u32 temp; pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp); + + intel_private.resource_valid = 1; if (!(temp & 0x1)) { - intel_alloc_chipset_flush_resource(); - intel_private.resource_valid = 1; - pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); + if (intel_alloc_chipset_flush_resource() == 0) + pci_write_config_dword(agp_bridge->dev, + I915_IFPADDR, + (intel_private.ifp_resource.start & 0xffffffff) | 0x1); } else { temp &= ~1; + intel_request_chipset_flush_resource(temp); - intel_private.resource_valid = 1; - intel_private.ifp_resource.start = temp; - intel_private.ifp_resource.end = temp + PAGE_SIZE; - ret = request_resource(&iomem_resource, &intel_private.ifp_resource); - /* some BIOSes reserve this area in a pnp some don't */ - if (ret) - intel_private.resource_valid = 0; } } static void intel_i965_g33_setup_chipset_flush(void) { u32 temp_hi, temp_lo; - int ret; pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi); pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo); + intel_private.resource_valid = 1; if (!(temp_lo & 0x1)) { - - intel_alloc_chipset_flush_resource(); - - intel_private.resource_valid = 1; - pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, - upper_32_bits(intel_private.ifp_resource.start)); - pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); + if (intel_alloc_chipset_flush_resource() == 0) { + pci_write_config_dword(agp_bridge->dev, + I965_IFPADDR + 4, + upper_32_bits(intel_private.ifp_resource.start)); + pci_write_config_dword(agp_bridge->dev, + I965_IFPADDR, + (intel_private.ifp_resource.start & 0xffffffff) | 0x1); + } } else { u64 l64; temp_lo &= ~0x1; l64 = ((u64)temp_hi << 32) | temp_lo; - intel_private.resource_valid = 1; - intel_private.ifp_resource.start = l64; - intel_private.ifp_resource.end = l64 + PAGE_SIZE; - ret = request_resource(&iomem_resource, &intel_private.ifp_resource); - /* some BIOSes reserve this area in a pnp some don't */ - if (ret) - intel_private.resource_valid = 0; + intel_request_chipset_flush_resource(l64); } }