From patchwork Mon Sep 13 22:35:14 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 176142 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id o8DMfnIb013603 for ; Mon, 13 Sep 2010 22:42:09 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7F0329E9B7 for ; Mon, 13 Sep 2010 15:41:49 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail.ffwll.ch (cable-static-49-187.intergga.ch [157.161.49.187]) by gabe.freedesktop.org (Postfix) with ESMTP id 242199EAFF for ; Mon, 13 Sep 2010 15:34:16 -0700 (PDT) Received: by mail.ffwll.ch (Postfix, from userid 1000) id 6D2A020C219; Tue, 14 Sep 2010 00:36:37 +0200 (CEST) X-Spam-ASN: X-Spam-Checker-Version: SpamAssassin 3.2.5 (2008-06-10) on orange.ffwll.ch X-Spam-Level: X-Spam-Hammy: 0.000-+--H*UA:git-send-email, 0.000-+--H*x:git-send-email, 0.000-+--1.7.1 X-Spam-Status: No, score=-4.4 required=6.0 tests=ALL_TRUSTED,BAYES_00 autolearn=ham version=3.2.5 X-Spam-Spammy: Received: from viiv.ffwll.ch (viiv.ffwll.ch [192.168.23.128]) by mail.ffwll.ch (Postfix) with ESMTP id 42D8E20C241; Tue, 14 Sep 2010 00:35:27 +0200 (CEST) Received: from daniel by viiv.ffwll.ch with local (Exim 4.72) (envelope-from ) id 1OvHcV-0008N6-1L; Tue, 14 Sep 2010 00:35:27 +0200 From: Daniel Vetter To: intel-gfx@lists.freedesktop.org Date: Tue, 14 Sep 2010 00:35:14 +0200 Message-Id: <1284417314-32070-18-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1284417314-32070-1-git-send-email-daniel.vetter@ffwll.ch> References: <1284417314-32070-1-git-send-email-daniel.vetter@ffwll.ch> Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 17/17] intel-gtt add a cleanup function for chipset specific stuff X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Mon, 13 Sep 2010 22:42:09 +0000 (UTC) diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index b0ba00c..616502b 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -76,6 +76,9 @@ struct intel_gtt_driver { unsigned int dma_mask_size : 8; /* Chipset specific GTT setup */ int (*setup)(void); + /* This should undo anything done in ->setup() save the unmapping + * of the mmio register file, that's done in the generic code. */ + void (*cleanup)(void); void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); /* Flags is a more or less chipset specific opaque value. * For chipsets that need to support old ums (non-gem) code, this @@ -733,12 +736,8 @@ static void intel_gtt_teardown_scratch_page(void) static void intel_gtt_cleanup(void) { - if (intel_private.i9xx_flush_page) - iounmap(intel_private.i9xx_flush_page); - if (intel_private.resource_valid) - release_resource(&intel_private.ifp_resource); - intel_private.ifp_resource.start = 0; - intel_private.resource_valid = 0; + intel_private.driver->cleanup(); + iounmap(intel_private.gtt); iounmap(intel_private.registers); @@ -769,6 +768,7 @@ static int intel_gtt_init(void) intel_private.gtt = ioremap(intel_private.gtt_bus_addr, gtt_map_size); if (!intel_private.gtt) { + intel_private.driver->cleanup(); iounmap(intel_private.registers); return -ENOMEM; } @@ -778,6 +778,7 @@ static int intel_gtt_init(void) /* we have to call this as early as possible after the MMIO base address is known */ intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries(); if (intel_private.base.gtt_stolen_entries == 0) { + intel_private.driver->cleanup(); iounmap(intel_private.registers); iounmap(intel_private.gtt); return -ENOMEM; @@ -811,7 +812,7 @@ static int intel_fake_agp_fetch_size(void) return 0; } -static void intel_i830_fini_flush(void) +static void i830_cleanup(void) { kunmap(intel_private.i8xx_page); intel_private.i8xx_flush_page = NULL; @@ -833,7 +834,7 @@ static void intel_i830_setup_flush(void) intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); if (!intel_private.i8xx_flush_page) - intel_i830_fini_flush(); + i830_cleanup(); } /* The chipset_flush interface needs to get data that has already been @@ -1175,6 +1176,16 @@ static void intel_i9xx_setup_flush(void) "can't ioremap flush page - no chipset flushing\n"); } +static void i9xx_cleanup(void) +{ + if (intel_private.i9xx_flush_page) + iounmap(intel_private.i9xx_flush_page); + if (intel_private.resource_valid) + release_resource(&intel_private.ifp_resource); + intel_private.ifp_resource.start = 0; + intel_private.resource_valid = 0; +} + static void i9xx_chipset_flush(void) { if (intel_private.i9xx_flush_page) @@ -1218,6 +1229,10 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry, writel(addr | pte_flags, intel_private.gtt + entry); } +static void gen6_cleanup(void) +{ +} + static int i9xx_setup(void) { u32 reg_addr; @@ -1312,6 +1327,7 @@ static const struct intel_gtt_driver i81x_gtt_driver = { static const struct intel_gtt_driver i8xx_gtt_driver = { .gen = 2, .setup = i830_setup, + .cleanup = i830_cleanup, .write_entry = i830_write_entry, .dma_mask_size = 32, .check_flags = i830_check_flags, @@ -1320,6 +1336,7 @@ static const struct intel_gtt_driver i8xx_gtt_driver = { static const struct intel_gtt_driver i915_gtt_driver = { .gen = 3, .setup = i9xx_setup, + .cleanup = i9xx_cleanup, /* i945 is the last gpu to need phys mem (for overlay and cursors). */ .write_entry = i830_write_entry, .dma_mask_size = 32, @@ -1330,6 +1347,7 @@ static const struct intel_gtt_driver g33_gtt_driver = { .gen = 3, .is_g33 = 1, .setup = i9xx_setup, + .cleanup = i9xx_cleanup, .write_entry = i965_write_entry, .dma_mask_size = 36, .check_flags = i830_check_flags, @@ -1339,6 +1357,7 @@ static const struct intel_gtt_driver pineview_gtt_driver = { .gen = 3, .is_pineview = 1, .is_g33 = 1, .setup = i9xx_setup, + .cleanup = i9xx_cleanup, .write_entry = i965_write_entry, .dma_mask_size = 36, .check_flags = i830_check_flags, @@ -1347,6 +1366,7 @@ static const struct intel_gtt_driver pineview_gtt_driver = { static const struct intel_gtt_driver i965_gtt_driver = { .gen = 4, .setup = i9xx_setup, + .cleanup = i9xx_cleanup, .write_entry = i965_write_entry, .dma_mask_size = 36, .check_flags = i830_check_flags, @@ -1355,6 +1375,7 @@ static const struct intel_gtt_driver i965_gtt_driver = { static const struct intel_gtt_driver g4x_gtt_driver = { .gen = 5, .setup = i9xx_setup, + .cleanup = i9xx_cleanup, .write_entry = i965_write_entry, .dma_mask_size = 36, .check_flags = i830_check_flags, @@ -1364,6 +1385,7 @@ static const struct intel_gtt_driver ironlake_gtt_driver = { .gen = 5, .is_ironlake = 1, .setup = i9xx_setup, + .cleanup = i9xx_cleanup, .write_entry = i965_write_entry, .dma_mask_size = 36, .check_flags = i830_check_flags, @@ -1372,6 +1394,7 @@ static const struct intel_gtt_driver ironlake_gtt_driver = { static const struct intel_gtt_driver sandybridge_gtt_driver = { .gen = 6, .setup = i9xx_setup, + .cleanup = gen6_cleanup, .write_entry = gen6_write_entry, .dma_mask_size = 40, .check_flags = gen6_check_flags,