From patchwork Mon Oct 4 23:31:25 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Lam X-Patchwork-Id: 230831 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id o94NVe59030797 for ; Mon, 4 Oct 2010 23:32:00 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4541B9EF9E for ; Mon, 4 Oct 2010 16:31:39 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-qy0-f170.google.com (mail-qy0-f170.google.com [209.85.216.170]) by gabe.freedesktop.org (Postfix) with ESMTP id 722BE9E79D for ; Mon, 4 Oct 2010 16:31:29 -0700 (PDT) Received: by qyk34 with SMTP id 34so1891288qyk.15 for ; Mon, 04 Oct 2010 16:31:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:mime-version:content-type; bh=uIFImRxXajryzVrdJB54lkRahHKZItjcmykHDKQOwms=; b=BeBUf1YllMtKHgofE0WoUuumf4SulGW0Y7aD6guyzKt+phcMgnTp9aKGqfEEBW8e6I ScQXloZ5XEn7JZY21ujRqqTCOI4YVJOrQNEAS+O6YcO+WTAHMxEEuJkDcj2+xKwGnYRh mBQjfBQlyyCJEK93nWPxQmipz4DAui9Fcq8pk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:mime-version :content-type; b=CQA569xdBL2sQgpELaEUJot4mGanWJFeaSZgDXdPAi3Y4szux/9ePSGPwauQNyZJEn f3e9krTlwMT3LYKAkZ/HT1i46etyk6kzEaZe4QJstUfq2jONdhIuc9G+7MErzqvZD8tq LJke7U6/U1sTmw97rDSkToyW3d8hqbQAxwX/I= Received: by 10.229.237.129 with SMTP id ko1mr7557098qcb.4.1286235088858; Mon, 04 Oct 2010 16:31:28 -0700 (PDT) Received: from localhost.localdomain ([128.237.250.101]) by mx.google.com with ESMTPS id t1sm6160821qcs.45.2010.10.04.16.31.27 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 04 Oct 2010 16:31:27 -0700 (PDT) From: Alexander Lam To: intel-gfx@lists.freedesktop.org, peng.li@intel.com Date: Mon, 4 Oct 2010 19:31:25 -0400 Message-Id: <1286235085-29700-1-git-send-email-lambchop468@gmail.com> X-Mailer: git-send-email 1.7.3.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] allow 945 to control self refresh automatically X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Mon, 04 Oct 2010 23:32:00 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 69c54c5..97f4d86 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3256,7 +3256,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, int planea_wm, planeb_wm; struct intel_watermark_params planea_params, planeb_params; unsigned long line_time_us; - int sr_clock, sr_entries = 0; + int sr_clock, sr_entries = 0, sr_enabled = 0; /* Create copies of the base settings for each pipe */ if (IS_CRESTLINE(dev) || IS_I945GM(dev)) @@ -3303,8 +3303,11 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, if (srwm < 0) srwm = 1; - if (IS_I945G(dev) || IS_I945GM(dev)) + if (IS_I945G(dev) || IS_I945GM(dev)){ I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); + printk("enable memory self refresh on 945\n"); + sr_enabled = 1; + } else if (IS_I915GM(dev)) { /* 915M has a smaller SRWM field */ I915_WRITE(FW_BLC_SELF, srwm & 0x3f); @@ -3313,6 +3316,8 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, } else { /* Turn off self refresh if both pipes are enabled */ if (IS_I945G(dev) || IS_I945GM(dev)) { + printk("disable memory self refresh on 945\n"); + sr_enabled = 0; I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); } else if (IS_I915GM(dev)) { @@ -3332,6 +3337,8 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, I915_WRITE(FW_BLC, fwater_lo); I915_WRITE(FW_BLC2, fwater_hi); + if (sr_enabled) + I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); } static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused, @@ -4828,7 +4835,6 @@ static void intel_idle_update(struct work_struct *work) struct drm_device *dev = dev_priv->dev; struct drm_crtc *crtc; struct intel_crtc *intel_crtc; - int enabled = 0; if (!i915_powersave) return; @@ -4842,16 +4848,11 @@ static void intel_idle_update(struct work_struct *work) if (!crtc->fb) continue; - enabled++; intel_crtc = to_intel_crtc(crtc); if (!intel_crtc->busy) intel_decrease_pllclock(crtc); } - if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) { - DRM_DEBUG_DRIVER("enable memory self refresh on 945\n"); - I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); - } mutex_unlock(&dev->struct_mutex); } @@ -4876,17 +4877,9 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) if (!drm_core_check_feature(dev, DRIVER_MODESET)) return; - if (!dev_priv->busy) { - if (IS_I945G(dev) || IS_I945GM(dev)) { - u32 fw_blc_self; - - DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); - fw_blc_self = I915_READ(FW_BLC_SELF); - fw_blc_self &= ~FW_BLC_SELF_EN; - I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); - } + if (!dev_priv->busy) dev_priv->busy = true; - } else + else mod_timer(&dev_priv->idle_timer, jiffies + msecs_to_jiffies(GPU_IDLE_TIMEOUT)); @@ -4898,14 +4891,6 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) intel_fb = to_intel_framebuffer(crtc->fb); if (intel_fb->obj == obj) { if (!intel_crtc->busy) { - if (IS_I945G(dev) || IS_I945GM(dev)) { - u32 fw_blc_self; - - DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); - fw_blc_self = I915_READ(FW_BLC_SELF); - fw_blc_self &= ~FW_BLC_SELF_EN; - I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); - } /* Non-busy -> busy, upclock */ intel_increase_pllclock(crtc); intel_crtc->busy = true;