From patchwork Sat Oct 9 07:32:26 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xiang, Haihao" X-Patchwork-Id: 243171 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id o997ZIwx005867 for ; Sat, 9 Oct 2010 07:35:39 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7DA619E8D5 for ; Sat, 9 Oct 2010 00:35:18 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id A5A2F9E971 for ; Sat, 9 Oct 2010 00:32:54 -0700 (PDT) Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga101.ch.intel.com with ESMTP; 09 Oct 2010 00:32:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.57,307,1283756400"; d="scan'208";a="334055534" Received: from xhh-ilk32.sh.intel.com (HELO localhost.localdomain) ([10.239.36.8]) by azsmga001.ch.intel.com with ESMTP; 09 Oct 2010 00:32:53 -0700 From: "Xiang, Haihao" To: intel-gfx@lists.freedesktop.org Date: Sat, 9 Oct 2010 15:32:26 +0800 Message-Id: <1286609550-16083-7-git-send-email-haihao.xiang@intel.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1286609550-16083-1-git-send-email-haihao.xiang@intel.com> References: <1286609550-16083-1-git-send-email-haihao.xiang@intel.com> Subject: [Intel-gfx] [PATCH 06/10] add support for data port write on Sandybridge. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Sat, 09 Oct 2010 07:35:50 +0000 (UTC) diff --git a/src/brw_structs.h b/src/brw_structs.h index 92a398e..6a29f37 100644 --- a/src/brw_structs.h +++ b/src/brw_structs.h @@ -1413,6 +1413,19 @@ struct brw_instruction } dp_write_gen5; struct { + GLuint binding_table_index:8; + GLuint msg_control:5; + GLuint msg_type:4; + GLuint send_commit_msg:1; + GLuint pad0:1; + GLuint header_present:1; + GLuint response_length:5; + GLuint msg_length:4; + GLuint pad1:2; + GLuint end_of_thread:1; + } dp_write_gen6; + + struct { GLuint opcode:1; GLuint requester_type:1; GLuint pad0:2; diff --git a/src/gram.y b/src/gram.y index 2dab7a2..d536625 100644 --- a/src/gram.y +++ b/src/gram.y @@ -650,7 +650,19 @@ msgtarget: NULL_TOKEN | WRITE LPAREN INTEGER COMMA INTEGER COMMA INTEGER COMMA INTEGER RPAREN { - if (gen_level == 5) { + if (gen_level == 6) { + $$.bits2.send_gen5.sfid = + BRW_MESSAGE_TARGET_DATAPORT_WRITE; + /* Sandybridge supports headerlesss message for render target write. + * Currently the GFX assembler doesn't support it. so the program must provide + * message header + */ + $$.bits3.generic_gen5.header_present = 1; + $$.bits3.dp_write_gen6.binding_table_index = $3; + $$.bits3.dp_write_gen6.msg_control = $5; + $$.bits3.dp_write_gen6.msg_type = $7; + $$.bits3.dp_write_gen6.send_commit_msg = $9; + } else if (gen_level == 5) { $$.bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_DATAPORT_WRITE; $$.bits3.generic_gen5.header_present = 1;