[5/5] render: use headerless render target write

Commit Message

Xiang, Haihao Nov. 1, 2010, 8:33 a.m. UTC

None

Patch

diff --git a/src/render_program/exa_wm_write.g6a b/src/render_program/exa_wm_write.g6a
index 27f91b5..55fe9c7 100644
--- a/src/render_program/exa_wm_write.g6a
+++ b/src/render_program/exa_wm_write.g6a
@@ -36,6 +36,7 @@  define(`slot_b_00',     `m6')
 define(`slot_b_01',     `m7')
 define(`slot_a_00',     `m8')
 define(`slot_a_01',     `m9')
+define(`data_port_msg_2_ind',	`2')
 
 mov (8) slot_r_00<1>F     src_sample_r_01<8,8,1>F { align1 };
 mov (8) slot_r_01<1>F     src_sample_r_23<8,8,1>F { align1 };
@@ -49,20 +50,17 @@  mov (8) slot_b_01<1>F     src_sample_b_23<8,8,1>F { align1 };
 mov (8) slot_a_00<1>F     src_sample_a_01<8,8,1>F { align1 };
 mov (8) slot_a_01<1>F     src_sample_a_23<8,8,1>F { align1 };
 
-/* pass payload in m0-m1 */
-mov (8) data_port_msg_0<1>UD    g0<8,8,1>UD { align1 };
-mov (8) data_port_msg_1<1>UD    g1<8,8,1>UD { align1 };
-
 /* write */
 send (16) 
-	data_port_msg_0_ind 
+	data_port_msg_2_ind 
 	acc0<1>UW 
 	null
 	write (
 	       0,  /* binding_table */
 	       16,  /* pixel scordboard clear, msg type simd16 single source */
 	       12,  /* render target write */
-	       0   /* no write commit message */
+	       0,   /* no write commit message */
+	       0  /* headerless render target write */
 	) 
 	mlen 10
 	rlen 0
diff --git a/src/render_program/exa_wm_write.g6b b/src/render_program/exa_wm_write.g6b
index 9db2129..e9e4d35 100644
--- a/src/render_program/exa_wm_write.g6b
+++ b/src/render_program/exa_wm_write.g6b
@@ -6,9 +6,7 @@ 
    { 0x00600001, 0x20e003be, 0x008d0260, 0x00000000 },
    { 0x00600001, 0x210003be, 0x008d0280, 0x00000000 },
    { 0x00600001, 0x212003be, 0x008d02a0, 0x00000000 },
-   { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 },
-   { 0x00600001, 0x20200022, 0x008d0020, 0x00000000 },
-   { 0x05800031, 0x24001cc8, 0x00000000, 0x94099000 },
+   { 0x05800031, 0x24001cc8, 0x00000040, 0x94019000 },
    { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
    { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
    { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },