drm/i915: Modify for pineview clock source

Commit Message

Bryan Freed Jan. 12, 2011, 9:38 p.m. UTC

None

Patch

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index b0b1200..a1c7269 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -555,9 +555,20 @@  parse_device_mapping(struct drm_i915_private *dev_priv,
 	return;
 }
 
+static int intel_bios_ssc_frequency(struct drm_device *dev, bool high_speed)
+{
+	if (IS_GEN2(dev))
+		return high_speed ? 66 : 48;
+	if (IS_GEN3(dev) || IS_GEN4(dev))
+		return high_speed ? 100 : 96;
+	return high_speed ? 120 : 100;
+}
+
 static void
 init_vbt_defaults(struct drm_i915_private *dev_priv)
 {
+	struct drm_device *dev = dev_priv->dev;
+
 	dev_priv->crt_ddc_pin = GMBUS_PORT_VGADDC;
 
 	/* LFP panel data */
@@ -570,7 +581,11 @@  init_vbt_defaults(struct drm_i915_private *dev_priv)
 	/* general features */
 	dev_priv->int_tv_support = 1;
 	dev_priv->int_crt_support = 1;
-	dev_priv->lvds_use_ssc = 0;
+
+	/* Default to using SSC */
+	dev_priv->lvds_use_ssc = 1;
+	dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
+	DRM_DEBUG("Set default to SSC at %dMHz\n", dev_priv->lvds_ssc_freq);
 
 	/* eDP data */
 	dev_priv->edp.bpp = 18;