From patchwork Fri Feb 4 21:37:08 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 532911 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p14LbXUg019967 for ; Fri, 4 Feb 2011 21:37:55 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 788569E9C4 for ; Fri, 4 Feb 2011 13:37:32 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from cpoproxy3-pub.bluehost.com (cpoproxy3-pub.bluehost.com [67.222.54.6]) by gabe.freedesktop.org (Postfix) with SMTP id 7F5A19E746 for ; Fri, 4 Feb 2011 13:37:12 -0800 (PST) Received: (qmail 22629 invoked by uid 0); 4 Feb 2011 21:37:11 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by cpoproxy3.bluehost.com with SMTP; 4 Feb 2011 21:37:11 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=virtuousgeek.org; h=Received:From:To:Cc:Subject:Date:Message-Id:X-Mailer:X-Identified-User; b=MqKNcWTJR69J0hiNEQ2Qfq0YebS/rEB9/wwptN1fwhhr49et2J3DXakps4GHby0QReWOQ8hQIPHe5w0H5Mb4Ns8hF2E1b+D1kJuiqauWXsjDve9/u1b0+JCcJuBUU5tN; Received: from c-67-174-193-198.hsd1.ca.comcast.net ([67.174.193.198] helo=localhost6.localdomain6) by box514.bluehost.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.69) (envelope-from ) id 1PlTL4-0005U0-4o; Fri, 04 Feb 2011 14:37:10 -0700 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Feb 2011 13:37:08 -0800 Message-Id: <1296855428-1206-1-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.7.2.3 X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.174.193.198 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH] drm/i915: the PCH reference clocks are global, so don't clobber unconditionally X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 04 Feb 2011 21:37:55 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fec84f4..a05fd76 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4520,6 +4520,84 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) return dev_priv->lvds_use_ssc && i915_panel_use_ssc; } +static void intel_update_dref(struct drm_i915_private *dev_priv) +{ + struct drm_device *dev = dev_priv->dev; + struct drm_mode_config *mode_config = &dev->mode_config; + struct intel_encoder *encoder; + struct intel_crtc *intel_crtc; + u32 temp; + bool lvds_on, edp_on, pch_edp_on = false, other_on; + + list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { + if (!encoder->base.crtc) + continue; + + intel_crtc = to_intel_crtc(encoder->base.crtc); + + if (!intel_crtc->active) + continue; + + switch (encoder->type) { + case INTEL_OUTPUT_LVDS: + lvds_on = true; + break; + case INTEL_OUTPUT_EDP: + edp_on = true; + if (!pch_edp_on) + pch_edp_on = intel_encoder_is_pch_edp(&encoder->base); + break; + default: + other_on = true; + break; + } + } + + /*XXX BIOS treats 16:31 as a mask for 0:15 */ + + temp = I915_READ(PCH_DREF_CONTROL); + + /* First clear the current state for output switching */ + temp &= ~DREF_SSC1_ENABLE; + temp &= ~DREF_SSC4_ENABLE; + temp &= ~DREF_SUPERSPREAD_SOURCE_MASK; + temp &= ~DREF_NONSPREAD_SOURCE_MASK; + temp &= ~DREF_SSC_SOURCE_MASK; + temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; + I915_WRITE(PCH_DREF_CONTROL, temp); + + POSTING_READ(PCH_DREF_CONTROL); + udelay(200); + + if ((lvds_on || edp_on) && intel_panel_use_ssc(dev_priv)) { + temp |= DREF_SSC_SOURCE_ENABLE; + if (edp_on) { + if (!pch_edp_on) { + /* Enable CPU source on CPU attached eDP */ + temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; + } else { + /* Enable SSC on PCH eDP if needed */ + temp |= DREF_SUPERSPREAD_SOURCE_ENABLE; + } + I915_WRITE(PCH_DREF_CONTROL, temp); + } + if (!dev_priv->display_clock_mode) + temp |= DREF_SSC1_ENABLE; + } + + if (other_on && dev_priv->display_clock_mode) + temp |= DREF_NONSPREAD_CK505_ENABLE; + else if (other_on) { + temp |= DREF_NONSPREAD_SOURCE_ENABLE; + if (edp_on && !pch_edp_on) + temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; + } + + I915_WRITE(PCH_DREF_CONTROL, temp); + POSTING_READ(PCH_DREF_CONTROL); + udelay(200); +} + static int intel_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode, @@ -4745,52 +4823,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, * PCH B stepping, previous chipset stepping should be * ignoring this setting. */ - if (HAS_PCH_SPLIT(dev)) { - /*XXX BIOS treats 16:31 as a mask for 0:15 */ - - temp = I915_READ(PCH_DREF_CONTROL); - - /* First clear the current state for output switching */ - temp &= ~DREF_SSC1_ENABLE; - temp &= ~DREF_SSC4_ENABLE; - temp &= ~DREF_SUPERSPREAD_SOURCE_MASK; - temp &= ~DREF_NONSPREAD_SOURCE_MASK; - temp &= ~DREF_SSC_SOURCE_MASK; - temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; - I915_WRITE(PCH_DREF_CONTROL, temp); - - POSTING_READ(PCH_DREF_CONTROL); - udelay(200); - - if ((is_lvds || has_edp_encoder) && - intel_panel_use_ssc(dev_priv)) { - temp |= DREF_SSC_SOURCE_ENABLE; - if (has_edp_encoder) { - if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) { - /* Enable CPU source on CPU attached eDP */ - temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; - } else { - /* Enable SSC on PCH eDP if needed */ - temp |= DREF_SUPERSPREAD_SOURCE_ENABLE; - } - I915_WRITE(PCH_DREF_CONTROL, temp); - } - if (!dev_priv->display_clock_mode) - temp |= DREF_SSC1_ENABLE; - } else { - if (dev_priv->display_clock_mode) - temp |= DREF_NONSPREAD_CK505_ENABLE; - else - temp |= DREF_NONSPREAD_SOURCE_ENABLE; - if (has_edp_encoder && - !intel_encoder_is_pch_edp(&has_edp_encoder->base)) - temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; - } - - I915_WRITE(PCH_DREF_CONTROL, temp); - POSTING_READ(PCH_DREF_CONTROL); - udelay(200); - } + if (HAS_PCH_SPLIT(dev)) + intel_update_dref(dev_priv); if (IS_PINEVIEW(dev)) { fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;