From patchwork Fri Feb 11 09:25:17 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 548941 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p1B9PfNP018904 for ; Fri, 11 Feb 2011 09:26:02 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CFBD19F006 for ; Fri, 11 Feb 2011 01:25:40 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (server109-228-6-236.live-servers.net [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id C81069E730 for ; Fri, 11 Feb 2011 01:25:22 -0800 (PST) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.66.37; Received: from arrandale.alporthouse.com (unverified [78.156.66.37]) by fireflyinternet.com (Firefly Internet SMTP) with ESMTP id 25587461-1500050 for multiple; Fri, 11 Feb 2011 09:26:20 +0000 From: Chris Wilson To: Jesse Barnes Date: Fri, 11 Feb 2011 09:25:17 +0000 Message-Id: <1297416317-9476-1-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 1.7.2.3 X-Originating-IP: 78.156.66.37 Cc: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH] drm/i915: Use TILECTL on SNB to detect swizzle mode X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 11 Feb 2011 09:26:02 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index 22a32b9..bc19fb2 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -92,7 +92,34 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; - if (IS_GEN5(dev) || IS_GEN6(dev)) { + if (IS_GEN6(dev)) { + /* TILECTL 0x10100 (uncore): + * [1:0] Address Swizzling for Tiled-Surfaces (SWZCTL): + * This register location is updated via GFX Driver prior to + * enabling DRAM accesses. The Driver needs to obtain the need + * for memory address swizzling via DRAM configuration registers + * and set the following bits. + * + * 00b - No Address Swizzling + * 01b - Address bit [6] needs to be swizzled for tiled surfaces + * 10b - Reserved + * 11b - Reserved + */ + printk(KERN_ERR "tilectl = %x\n", I915_READ(GEN6_TILECTL)); + switch (I915_READ(GEN6_TILECTL) & 0x3) { + default: + DRM_ERROR("unknown swizzle mode for tiled surfaces: %x\n", + I915_READ(GEN6_TILECTL)); + case 0: + swizzle_x = I915_BIT_6_SWIZZLE_NONE; + swizzle_y = I915_BIT_6_SWIZZLE_NONE; + break; + case 1: + swizzle_x = I915_BIT_6_SWIZZLE_9_10; + swizzle_y = I915_BIT_6_SWIZZLE_9; + break; + } + } else if (IS_GEN5(dev)) { /* On Ironlake whatever DRAM config, GPU always do * same swizzling setup. */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 15d94c6..49bae1a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2781,8 +2781,11 @@ #define DISP_ARB_CTL 0x45000 #define DISP_TILE_SURFACE_SWIZZLING (1<<13) +#define DISP_TILE_MASK (3<<13) #define DISP_FBC_WM_DIS (1<<15) +#define GEN6_TILECTL 0x101000 + /* PCH */ /* south display engine interrupt */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3b00653..94b6030 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4457,10 +4457,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, intel_wait_for_vblank(dev, pipe); + /* enable address swizzle for tiling scanout */ if (IS_GEN5(dev)) { - /* enable address swizzle for tiling buffer */ - temp = I915_READ(DISP_ARB_CTL); + temp = I915_READ(DISP_ARB_CTL) & ~DISP_TILE_MASK; I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); + } else if (IS_GEN6 (dev)) { + temp = I915_READ(DISP_ARB_CTL) & ~DISP_TILE_MASK; + temp |= (I915_READ(GEN6_TILECTL) & 0x3) << 13; + I915_WRITE(DISP_ARB_CTL, temp); } I915_WRITE(DSPCNTR(plane), dspcntr);