From patchwork Tue Mar 15 04:52:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 635061 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p2F61NTZ004857 for ; Tue, 15 Mar 2011 06:01:44 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 085089E959 for ; Mon, 14 Mar 2011 23:01:23 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Tue, 15 Mar 2011 06:01:44 +0000 (UTC) X-Greylist: delayed 349 seconds by postgrey-1.31 at gabe; Mon, 14 Mar 2011 23:01:01 PDT Received: from cloud01.chad-versace.us (184-106-247-128.static.cloud-ips.com [184.106.247.128]) by gabe.freedesktop.org (Postfix) with ESMTP id D57469E710 for ; Mon, 14 Mar 2011 23:01:01 -0700 (PDT) Received: from localhost.localdomain (unknown [67.208.96.87]) by cloud01.chad-versace.us (Postfix) with ESMTPSA id 5E9BB1D4008; Tue, 15 Mar 2011 05:55:37 +0000 (UTC) From: Ben Widawsky To: intel-gfx@lists.freedesktop.org Date: Mon, 14 Mar 2011 21:52:23 -0700 Message-Id: <1300164743-4577-1-git-send-email-ben@bwidawsk.net> X-Mailer: git-send-email 1.7.3.4 Subject: [Intel-gfx] [PATCH] drm/i915: Re-enable rc6 w/fix X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 22ec066..e3c808d 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -49,7 +49,7 @@ module_param_named(powersave, i915_powersave, int, 0600); unsigned int i915_semaphores = 0; module_param_named(semaphores, i915_semaphores, int, 0600); -unsigned int i915_enable_rc6 = 0; +unsigned int i915_enable_rc6 = 1; module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); unsigned int i915_lvds_downclock = 0; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 49fb54f..5675610 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6616,7 +6616,7 @@ void ironlake_enable_rc6(struct drm_device *dev) * GPU can automatically power down the render unit if given a page * to save state. */ - ret = BEGIN_LP_RING(6); + ret = BEGIN_LP_RING(10); if (ret) { ironlake_teardown_rc6(dev); return; @@ -6630,12 +6630,15 @@ void ironlake_enable_rc6(struct drm_device *dev) MI_RESTORE_EXT_STATE_EN | MI_RESTORE_INHIBIT); OUT_RING(MI_SUSPEND_FLUSH); - OUT_RING(MI_NOOP); OUT_RING(MI_FLUSH); + OUT_RING(MI_LOAD_REGISTER_IMM(2)); + OUT_RING(PWRCTXA); + OUT_RING(dev_priv->pwrctx->gtt_offset | PWRCTX_EN); + OUT_RING(RSTDBYCTL); + OUT_RING(I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); ADVANCE_LP_RING(); - I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); - I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); + DRM_DEBUG_DRIVER("pwrctx offset: %p", dev_priv->pwrctx->gtt_offset); }