@@ -49,7 +49,7 @@ module_param_named(powersave, i915_powersave, int, 0600);
unsigned int i915_semaphores = 0;
module_param_named(semaphores, i915_semaphores, int, 0600);
-unsigned int i915_enable_rc6 = 0;
+unsigned int i915_enable_rc6 = 1;
module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
unsigned int i915_lvds_downclock = 0;
@@ -6616,7 +6616,7 @@ void ironlake_enable_rc6(struct drm_device *dev)
* GPU can automatically power down the render unit if given a page
* to save state.
*/
- ret = BEGIN_LP_RING(6);
+ ret = BEGIN_LP_RING(10);
if (ret) {
ironlake_teardown_rc6(dev);
return;
@@ -6630,12 +6630,15 @@ void ironlake_enable_rc6(struct drm_device *dev)
MI_RESTORE_EXT_STATE_EN |
MI_RESTORE_INHIBIT);
OUT_RING(MI_SUSPEND_FLUSH);
- OUT_RING(MI_NOOP);
OUT_RING(MI_FLUSH);
+ OUT_RING(MI_LOAD_REGISTER_IMM(2));
+ OUT_RING(PWRCTXA);
+ OUT_RING(dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
+ OUT_RING(RSTDBYCTL);
+ OUT_RING(I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
ADVANCE_LP_RING();
- I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
- I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
+ DRM_DEBUG_DRIVER("pwrctx offset: %p", dev_priv->pwrctx->gtt_offset);
}