From patchwork Fri Mar 18 22:35:16 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 645631 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p2IMahSD018626 for ; Fri, 18 Mar 2011 22:37:03 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 65D119ECD9 for ; Fri, 18 Mar 2011 15:36:43 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (server109-228-6-236.live-servers.net [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id 1515D9EB0F for ; Fri, 18 Mar 2011 15:35:36 -0700 (PDT) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.66.37; Received: from arrandale.alporthouse.com (unverified [78.156.66.37]) by fireflyinternet.com (Firefly Internet SMTP) with ESMTP id 29546811-1500050 for multiple; Fri, 18 Mar 2011 22:36:55 +0000 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Fri, 18 Mar 2011 22:35:16 +0000 Message-Id: <1300487719-26578-2-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1300487719-26578-1-git-send-email-chris@chris-wilson.co.uk> References: <1300487719-26578-1-git-send-email-chris@chris-wilson.co.uk> X-Originating-IP: 78.156.66.37 Cc: Andy Whitcroft Subject: [Intel-gfx] [PATCH 1/4] drm/i915: Track fence setup separately from fenced object lifetime X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 18 Mar 2011 22:37:03 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4496505..bcbcb53 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -129,6 +129,7 @@ struct drm_i915_master_private { struct drm_i915_fence_reg { struct list_head lru_list; struct drm_i915_gem_object *obj; + struct intel_ring_buffer *setup_ring; uint32_t setup_seqno; }; @@ -818,7 +819,6 @@ struct drm_i915_gem_object { /** Breadcrumb of last fenced GPU access to the buffer. */ uint32_t last_fenced_seqno; - struct intel_ring_buffer *last_fenced_ring; /** Current tiling stride for the object, if it's tiled. */ uint32_t stride; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index c5dfb59..ef84c13 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1640,7 +1640,6 @@ i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); obj->last_fenced_seqno = seqno; - obj->last_fenced_ring = ring; reg = &dev_priv->fence_regs[obj->fence_reg]; list_move_tail(®->lru_list, &dev_priv->mm.fence_list); @@ -1684,6 +1683,8 @@ i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) i915_gem_object_move_off_active(obj); obj->fenced_gpu_access = false; + obj->last_fenced_seqno = 0; + obj->active = 0; obj->pending_gpu_write = false; drm_gem_object_unreference(&obj->base); @@ -1849,7 +1850,6 @@ static void i915_gem_reset_fences(struct drm_device *dev) reg->obj->fence_reg = I915_FENCE_REG_NONE; reg->obj->fenced_gpu_access = false; reg->obj->last_fenced_seqno = 0; - reg->obj->last_fenced_ring = NULL; i915_gem_clear_fence_reg(dev, reg); } } @@ -2450,7 +2450,7 @@ i915_gem_object_flush_fence(struct drm_i915_gem_object *obj, if (obj->fenced_gpu_access) { if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { - ret = i915_gem_flush_ring(obj->last_fenced_ring, + ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); if (ret) return ret; @@ -2459,17 +2459,15 @@ i915_gem_object_flush_fence(struct drm_i915_gem_object *obj, obj->fenced_gpu_access = false; } - if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) { - if (!ring_passed_seqno(obj->last_fenced_ring, - obj->last_fenced_seqno)) { - ret = i915_wait_request(obj->last_fenced_ring, + if (obj->last_fenced_seqno && pipelined != obj->ring) { + if (!ring_passed_seqno(obj->ring, obj->last_fenced_seqno)) { + ret = i915_wait_request(obj->ring, obj->last_fenced_seqno); if (ret) return ret; } obj->last_fenced_seqno = 0; - obj->last_fenced_ring = NULL; } /* Ensure that all CPU reads are completed before installing a fence @@ -2536,8 +2534,8 @@ i915_find_fence_reg(struct drm_device *dev, first = reg; if (!pipelined || - !reg->obj->last_fenced_ring || - reg->obj->last_fenced_ring == pipelined) { + !reg->obj->last_fenced_seqno || + reg->obj->ring == pipelined) { avail = reg; break; } @@ -2589,30 +2587,23 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj, if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) pipelined = NULL; - if (pipelined) { - reg->setup_seqno = - i915_gem_next_request_seqno(pipelined); - obj->last_fenced_seqno = reg->setup_seqno; - obj->last_fenced_ring = pipelined; - } - goto update; } if (!pipelined) { if (reg->setup_seqno) { - if (!ring_passed_seqno(obj->last_fenced_ring, + if (!ring_passed_seqno(reg->setup_ring, reg->setup_seqno)) { - ret = i915_wait_request(obj->last_fenced_ring, + ret = i915_wait_request(reg->setup_ring, reg->setup_seqno); if (ret) return ret; } reg->setup_seqno = 0; + reg->setup_ring = NULL; } - } else if (obj->last_fenced_ring && - obj->last_fenced_ring != pipelined) { + } else if (obj->last_fenced_seqno && obj->ring != pipelined) { ret = i915_gem_object_flush_fence(obj, pipelined); if (ret) return ret; @@ -2647,9 +2638,13 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj, pipelined = NULL; old->fence_reg = I915_FENCE_REG_NONE; - old->last_fenced_ring = pipelined; - old->last_fenced_seqno = - pipelined ? i915_gem_next_request_seqno(pipelined) : 0; + old->last_fenced_seqno = 0; + if (pipelined) { + old->last_fenced_seqno = + i915_gem_next_request_seqno(pipelined); + i915_gem_object_move_to_active(old, pipelined, + old->last_fenced_seqno); + } drm_gem_object_unreference(&old->base); } else if (obj->last_fenced_seqno == 0) @@ -2658,13 +2653,13 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj, reg->obj = obj; list_move_tail(®->lru_list, &dev_priv->mm.fence_list); obj->fence_reg = reg - dev_priv->fence_regs; - obj->last_fenced_ring = pipelined; +update: reg->setup_seqno = pipelined ? i915_gem_next_request_seqno(pipelined) : 0; - obj->last_fenced_seqno = reg->setup_seqno; + reg->setup_ring = pipelined; -update: + obj->last_fenced_seqno = reg->setup_seqno; obj->tiling_changed = false; switch (INTEL_INFO(dev)->gen) { case 6: @@ -2721,6 +2716,7 @@ i915_gem_clear_fence_reg(struct drm_device *dev, list_del_init(®->lru_list); reg->obj = NULL; reg->setup_seqno = 0; + reg->setup_ring = NULL; } /**