From patchwork Fri Mar 18 23:12:46 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 645701 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p2INE9go005354 for ; Fri, 18 Mar 2011 23:14:30 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 334879E9E2 for ; Fri, 18 Mar 2011 16:14:09 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from cloud01.chad-versace.us (184-106-247-128.static.cloud-ips.com [184.106.247.128]) by gabe.freedesktop.org (Postfix) with ESMTP id 1BBCF9E7E8 for ; Fri, 18 Mar 2011 16:12:59 -0700 (PDT) Received: from localhost.localdomain (unknown [67.208.96.87]) by cloud01.chad-versace.us (Postfix) with ESMTPSA id C31D11D4078; Fri, 18 Mar 2011 23:13:27 +0000 (UTC) From: Ben Widawsky To: intel-gfx@lists.freedesktop.org Date: Fri, 18 Mar 2011 16:12:46 -0700 Message-Id: <1300489968-8574-3-git-send-email-ben@bwidawsk.net> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1300489968-8574-1-git-send-email-ben@bwidawsk.net> References: <1300489968-8574-1-git-send-email-ben@bwidawsk.net> Subject: [Intel-gfx] [PATCH 2/4] drm/i915: fix rc6 initialization on Ironlake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 18 Mar 2011 23:14:30 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 790af25..c1e9c30 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6603,14 +6603,27 @@ static int ironlake_setup_rc6(struct drm_device *dev) return 0; } +static int ironlake_wait_set_context(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_ring_buffer *ring = LP_RING(dev_priv); + int ret = -EAGAIN; + + ret = wait_for((I915_READ_HEAD(ring) == I915_READ_TAIL(ring)), 1000); + if (ret && atomic_read(&dev_priv->mm.wedged)) { + ret = -EIO; + } else if (!ret) { /* head == tail */ + ret = 0; + } + + return ret; +} + void ironlake_enable_rc6(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; int ret; - /* rc6 disabled by default due to repeated reports of hanging during - * boot and resume. - */ if (!i915_enable_rc6) return; @@ -6640,6 +6653,19 @@ void ironlake_enable_rc6(struct drm_device *dev) OUT_RING(MI_FLUSH); ADVANCE_LP_RING(); + /* + * Wait for the command parser to advance past MI_SET_CONTEXT. The HW + * does an implicit flush, combined with MI_FLUSH above, it should be + * safe to assume that renderctx is valid + */ + ret = ironlake_wait_set_context(dev); + if (ret) { + if (ret == -EAGAIN) + DRM_ERROR("rc6 switch took too long, freeing the bo"); + ironlake_teardown_rc6(dev, true); + return; + } + I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); }