From patchwork Tue Mar 22 13:51:59 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 652681 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p2MDt7jV006994 for ; Tue, 22 Mar 2011 13:55:28 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ECC429ED98 for ; Tue, 22 Mar 2011 06:55:06 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (server109-228-6-236.live-servers.net [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id AC5F09ECC4 for ; Tue, 22 Mar 2011 06:52:12 -0700 (PDT) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.66.37; Received: from arrandale.alporthouse.com (unverified [78.156.66.37]) by fireflyinternet.com (Firefly Internet SMTP) with ESMTP id 29827567-1500050 for multiple; Tue, 22 Mar 2011 13:54:56 +0000 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Tue, 22 Mar 2011 13:51:59 +0000 Message-Id: <1300801920-23130-15-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1300801920-23130-1-git-send-email-chris@chris-wilson.co.uk> References: <1300801920-23130-1-git-send-email-chris@chris-wilson.co.uk> X-Originating-IP: 78.156.66.37 Subject: [Intel-gfx] [PATCH 14/15] drm/i915: Cleanup flush|invalidate domain tracking for set_to_gpu X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Tue, 22 Mar 2011 13:55:28 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 3c54911..d04bd3d 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -36,7 +36,6 @@ struct change_domains { uint32_t invalidate_domains; uint32_t flush_domains; - uint32_t flush_rings; uint32_t flips; }; @@ -156,7 +155,7 @@ i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj, struct intel_ring_buffer *ring, struct change_domains *cd) { - uint32_t invalidate_domains = 0, flush_domains = 0; + uint32_t flush = 0; /* * If the object isn't moving to a new write domain, @@ -172,22 +171,17 @@ i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj, * write domain */ if (obj->base.write_domain && - (obj->base.write_domain != obj->base.pending_read_domains || - obj->ring != ring)) { - flush_domains |= obj->base.write_domain; - invalidate_domains |= - obj->base.pending_read_domains & ~obj->base.write_domain; - } + obj->base.write_domain != obj->base.pending_read_domains) + flush = obj->base.write_domain; /* * Invalidate any read caches which may have * stale data. That is, any new read domains. */ - invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains; - if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) + if (flush & I915_GEM_DOMAIN_CPU) i915_gem_clflush_object(obj); /* blow away mappings if mapped through GTT */ - if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT) + if (flush & I915_GEM_DOMAIN_GTT) i915_gem_release_mmap(obj); if (obj->base.pending_write_domain) @@ -199,15 +193,12 @@ i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj, * write_domains). So if we have a current write domain that we * aren't changing, set pending_write_domain to that. */ - if (flush_domains == 0 && obj->base.pending_write_domain == 0) + if (flush == 0 && obj->base.pending_write_domain == 0) obj->base.pending_write_domain = obj->base.write_domain; - cd->invalidate_domains |= invalidate_domains; - cd->flush_domains |= flush_domains; - if (flush_domains & I915_GEM_GPU_DOMAINS) - cd->flush_rings |= obj->ring->id; - if (invalidate_domains & I915_GEM_GPU_DOMAINS) - cd->flush_rings |= ring->id; + cd->flush_domains |= flush; + cd->invalidate_domains |= + obj->base.pending_read_domains & ~obj->base.read_domains; } struct eb_objects { @@ -710,35 +701,6 @@ err: } static int -i915_gem_execbuffer_flush(struct drm_device *dev, - uint32_t invalidate_domains, - uint32_t flush_domains, - uint32_t flush_rings) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - int i, ret; - - if (flush_domains & I915_GEM_DOMAIN_CPU) - intel_gtt_chipset_flush(); - - if (flush_domains & I915_GEM_DOMAIN_GTT) - wmb(); - - if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { - for (i = 0; i < I915_NUM_RINGS; i++) - if (flush_rings & (1 << i)) { - ret = i915_gem_flush_ring(&dev_priv->ring[i], - invalidate_domains, - flush_domains); - if (ret) - return ret; - } - } - - return 0; -} - -static int i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips) { u32 plane, flip_mask; @@ -783,14 +745,11 @@ i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, list_for_each_entry(obj, objects, exec_list) i915_gem_object_set_to_gpu_domain(obj, ring, &cd); - if (cd.invalidate_domains | cd.flush_domains) { - ret = i915_gem_execbuffer_flush(ring->dev, - cd.invalidate_domains, - cd.flush_domains, - cd.flush_rings); - if (ret) - return ret; - } + if (cd.flush_domains & I915_GEM_DOMAIN_CPU) + intel_gtt_chipset_flush(); + + if (cd.flush_domains & I915_GEM_DOMAIN_GTT) + wmb(); if (cd.flips) { ret = i915_gem_execbuffer_wait_for_flips(ring, cd.flips); @@ -804,7 +763,9 @@ i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, return ret; } - return 0; + return i915_gem_flush_ring(ring, + cd.invalidate_domains, + cd.flush_domains); } static bool