From patchwork Tue Mar 29 23:59:54 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Anholt X-Patchwork-Id: 672512 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p2U033dX024027 for ; Wed, 30 Mar 2011 00:03:23 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EE6FC9EB76 for ; Tue, 29 Mar 2011 17:03:02 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from annarchy.freedesktop.org (annarchy.freedesktop.org [131.252.210.176]) by gabe.freedesktop.org (Postfix) with ESMTP id 015DE9E92A; Tue, 29 Mar 2011 17:00:01 -0700 (PDT) Received: from pollan.anholt.net (annarchy.freedesktop.org [127.0.0.1]) by annarchy.freedesktop.org (Postfix) with ESMTP id CCCE013000C; Tue, 29 Mar 2011 17:00:00 -0700 (PDT) Received: by pollan.anholt.net (Postfix, from userid 1000) id 05A5932C055; Tue, 29 Mar 2011 16:59:58 -0700 (PDT) From: Eric Anholt To: intel-gfx@lists.freedesktop.org Date: Tue, 29 Mar 2011 16:59:54 -0700 Message-Id: <1301443195-10721-6-git-send-email-eric@anholt.net> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1301443195-10721-1-git-send-email-eric@anholt.net> References: <1301443195-10721-1-git-send-email-eric@anholt.net> Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Use the uncached domain for the display planes v2 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 30 Mar 2011 00:03:23 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 8389b03..de9a446 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3062,6 +3062,19 @@ i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj, return ret; } + /* The display engine is not coherent with the LLC cache on gen6. As + * a result, we make sure that the pinning that is about to occur is + * done with uncached PTEs. This is lowest common denominator for all + * chipsets. + * + * However for gen6+, we could do better by using the GFDT bit instead + * of uncaching, which would allow us to flush all the LLC-cached data + * with that bit in the PTE to main memory with just one PIPE_CONTROL. + */ + ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); + if (ret) + return ret; + i915_gem_object_flush_cpu_write_domain(obj); old_read_domains = obj->base.read_domains;