From patchwork Tue Apr 12 20:31:54 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 702121 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3CKkLV2006240 for ; Tue, 12 Apr 2011 20:46:41 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 214149EFBF for ; Tue, 12 Apr 2011 13:46:21 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 730739E9A9 for ; Tue, 12 Apr 2011 13:32:57 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 12 Apr 2011 13:32:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.64,199,1301900400"; d="scan'208";a="627582321" Received: from unknown (HELO cantiga.alporthouse.com) ([10.255.16.172]) by orsmga002.jf.intel.com with ESMTP; 12 Apr 2011 13:32:56 -0700 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Tue, 12 Apr 2011 21:31:54 +0100 Message-Id: <1302640318-23165-27-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1302640318-23165-1-git-send-email-chris@chris-wilson.co.uk> References: <1302640318-23165-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 26/30] drm/i915: Maintain fenced gpu access until we flush the fence X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Tue, 12 Apr 2011 20:46:41 +0000 (UTC) We only want to mark the transition from unfenced GPU access by an execbuffer, so that we are forced to flush any pending writes through the fence before updating the register. Signed-off-by: Chris Wilson Reviewed-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 20a4cc5..a07911f 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -911,7 +911,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *objects, obj->base.read_domains = obj->base.pending_read_domains; obj->base.write_domain = obj->base.pending_write_domain; - obj->fenced_gpu_access = obj->pending_fenced_gpu_access; + obj->fenced_gpu_access |= obj->pending_fenced_gpu_access; i915_gem_object_move_to_active(obj, ring, seqno); if (obj->base.write_domain) {